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Cypress Semiconductor Electronic Components Datasheet

Z9960 Datasheet

200 MHz Multi-Output Zero Delay Buffer

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Z9960
2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer
Features
• 2.5V or 3.3V operation
• Output frequency up to 200 MHz
Supports PowerPC, and Pentium® processors
• 21 clock outputs: drive up to 42 clock lines
• LVPECL or LVCMOS/LVTTL clock input
• Output-to-output skew < 150 ps
• Split 2.5V/3.3V outputs
• Spread spectrum compatible
• Glitch-free output clocks transitioning
• Output disable control
• Pin-compatible with MPC9600
• Industrial temperature range: –40°C to +85°C
• 48-pin LQFP package
Block Diagram
Table 1. Frequency Table[1]
SS
EE
LL
A QA B
0 VCO/2 0
1 VCO/4 1
QB
VCO/2
VCO/4
S
E
L
C
0
1
QC
VCO/2
VCO/4
F
B
_
S
E
L
0
1
FB_OUT
VCO/8
VCO/12
Pin Configuration
REF_SEL
TCLK
PECL_CLK
PECL_CLK#
FB_IN
SELA
SELB
AVDD
PLL
0
1
REF
FB
0
1
/2
/4
/8
/12
A
0
1
DQ
B
0
1
DQ
SELC
C
0
1
DQ
OE#
FB
0
1
DQ
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
FB_OUT
VSS
TCLK
PECL_CLK
PECL_CLK#
VDD
REF_SEL
FB_SEL
AVDD
SELA
SELB
SELC
VSSC
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5
6
Z9960
32
31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
VSSA
FB_OUT
QB0
QB1
VDDB
QB2
QB3
VSSB
QB4
QB5
QB6
VDDB
FB_SEL
Note:
1. Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1), or 25 MHz to 50 MHz (FB_SEL = 0).
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07087 Rev. *C
Revised May 03, 2004


Cypress Semiconductor Electronic Components Datasheet

Z9960 Datasheet

200 MHz Multi-Output Zero Delay Buffer

No Preview Available !

www.DataSheet4U.com
Z9960
Pin Definition
Pin Name
PECL_CLK
PECL_CLK#
TCLK
QA(6:0)
QB(6:0)
QC(6:0)
FB_OUT
No.
3
4
2
38, 39, 40, 42,
43, 45, 46
26, 27, 28, 30,
31, 33, 34
15, 16, 18, 19,
21, 22, 23
35
SELA
SELB
SELC
FB_SEL
FB_IN
REF_SEL
OE#
VDDA
VDDB
VDDC
VDD
AVDD
VSSA
VSSB
VSSC
VSS
9
10
11
7
47
6
14
37, 44
25, 32
13, 20
5
8
36, 41
24, 29
12, 17
1, 48
Type
I, PD
I, PU
I, PD
O
VDDA
O
VDDB
O
VDDC
O
VDD
I, PU
I, PU
I, PU
I, PU
I, PD
I, PU
I, PD
Pin Description
PECL Clock Input.
PECL Clock Input.
External Reference/Test Clock Input.
Clock Outputs. See Table 1 for frequency selections.
Clock Outputs. See Table 1 for frequency selections.
Clock Outputs. See Table 1 for frequency selections.
Feedback Clock Output. Connect to FB_IN for normal operation. The divider
ratio for this output is set by FB_SEL; see Table 1. A bypass delay capacitor at
this output will control Input Reference/ Output Banks phase relationships.
Frequency Select Inputs. These inputs select the divider ratio at QA(0:6)
outputs. See Table 1.
Frequency Select Inputs. These inputs select the divider ratio at QB(0:6)
outputs. See Table 1.
Frequency Select Inputs. These inputs select the divider ratio at QC(0:6)
outputs. See Table 1.
Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output.
See Table 1.
Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
Reference Select Input. When high, the PECL clock is selected. And when low,
TCLK is the reference clock.
Output Enable Input. When asserted low, enables all of the outputs. When
pulled high, disables to high impedance all of the outputs except FB_OUT.
Power Supply for Bank A Clock Buffers.
Power Supply for Bank B Clock Buffers.
Power Supply for Bank C Clock Buffers.
Power Supply for Core
Power Supply for PLL. When AVDD is set low, PLL is bypassed.
Common Ground for Bank A.
Common Ground for Bank B.
Common Ground for Bank C.
Common Ground.
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors
are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Document #: 38-07087 Rev. *C
Page 2 of 7


Part Number Z9960
Description 200 MHz Multi-Output Zero Delay Buffer
Maker Cypress Semiconductor
Total Page 7 Pages
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