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Cypress Semiconductor Electronic Components Datasheet

Z9973 Datasheet

Multi-Output Zero Delay Buffer

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Z9973
3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Features
• Output frequency up to 125 MHz
• 12 clock outputs: frequency configurable
• 350 ps max output-to-output skew
• Configurable output disable
• Two reference clock inputs for dynamic toggling
• Oscillator or PECL reference input
• Spread spectrum-compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin-compatible with MPC973
• Industrial temperature range: –40°C to +85°C
• 52-pin TQFP package
Block Diagram
PECL_CLK
PECL_CLK#
VCO_SEL
PLL_EN
REF_SEL
TCLK0
TCLK1
TCLK_SEL
FB_IN
0
1
Phase
Detector
VCO
LPF
0
1
FB_SEL2
MR#/OE
Power-On
Reset
SELA(0,1)
2
SELB(0,1)
SELC(0,1)
2
2
FB_SEL(0,1)
2
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
Data Generator
0
/2 1
SCLK
SDATA
Output Disable
Circuitry
12
INV_CLK
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
Table 1. Frequency Table[1]
VC0_SEL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FB_SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FB_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FB_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FVC0
8x
12x
16x
20x
16x
24x
32x
40x
4x
6x
8x
10x
8x
12x
16x
20x
Note:
1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz.
.
Pin Configuration
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
VDD
52 51 50 49 48 47 46 45 44 43 42 41 40
1 39
2 38
3 37
4 36
5 35
6 34
7 Z9973 33
8 32
9 31
10 30
11 29
12 28
13 27
14 15 16 17 18 19 20 21 22 23 24 25 26
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
SYNC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07089 Rev. *D
Revised December 21, 2002


Cypress Semiconductor Electronic Components Datasheet

Z9973 Datasheet

Multi-Output Zero Delay Buffer

No Preview Available !

www.DataSheet4U.com
Z9973
Pin Description [2]
Pin Number Pin Name PWR I/O Type
Pin Description
11 PECL_CLK
I PU PECL Clock Input.
12 PECL_CLK#
I PD PECL Clock Input.
9 TCLK0
I PU External Reference/Test Clock Input.
10 TCLK1
I PU External Reference/Test Clock Input.
44, 46, 48, 50 QA(3:0) VDDC O
Clock Outputs. See Table 2 for frequency selections.
32, 34, 36, 38 QB(3:0) VDDC O
Clock Outputs. See Table 2 for frequency selections.
16, 18, 21, 23 QC(3:0) VDDC O
Clock Outputs. See Table 2 for frequency selections.
29 FB_OUT VDDC O Feedback Clock Output. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL(0:2). See Table 1. A bypass
delay capacitor at this output will control Input Reference/ Output Banks
phase relationships.
25
SYNC VDDC O
Synchronous Pulse Output. This output is used for system synchroni-
zation. The rising edge of the output pulse is in sync with both the rising
edges of QA (0:3) and QC(0:3) output clocks regardless of the divider ratios
selected.
42, 43
SELA(1,0)
I PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:3)
outputs. See Table 2.
40, 41
SELB(1,0)
I PU Frequency Select Inputs. These inputs select the divider ratio at QB(0:3)
outputs. See Table 2.
19, 20
SELC(1,0)
I PU Frequency Select Inputs. These inputs select the divider ratio at QC(0:3)
outputs. See Table 2.
5, 26, 27 FB_SEL(2:0)
I PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
output. See Table 1.
52 VCO_SEL
I PU VCO Divider Select Input. When set LOW, the VCO output is divided by
2. When set HIGH, the divider is bypassed. See Table 1.
31 FB_IN
I PU Feedback Clock Input. Connect to FB_OUT for accessing the
phase-locked loop (PLL).
6 PLL_EN
I PU PLL Enable Input. When asserted HIGH, PLL is enabled. And when LOW,
PLL is bypassed.
7 REF_SEL
I PU Reference Select Input. When HIGH, the crystal oscillator is selected. And
when LOW, TCLK (0,1) is the reference clock.
8 TCLK_SEL
I PU TCLK Select Input. When LOW, TCLK0 is selected and when HIGH TCLK1
is selected.
2 MR#/OE
I PU Master Reset/Output Enable Input. When asserted LOW, resets all of the
internal flip-flops and also disables all of the outputs. When pulled HIGH,
releases the internal flip-flops from reset and enables all of the outputs.
14 INV_CLK
I PU Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted. When
set LOW, the inverter is bypassed.
3 SCLK
I PU Serial Clock Input. Clocks data at SDATA into the internal register.
4 SDATA
I PU Serial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
17, 22, 28,
33,37, 45, 49
VDDC
3.3V Power Supply for Output Clock Buffers.
13 VDD
3.3V Supply for PLL.
1, 15, 24, 30,
35, 39, 47, 51
VSS
Common Ground.
Note:
2. A bypass capacitor (0.1 µF) should be placed as close as possible to each positive power (< 0.2). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Document #: 38-07089 Rev. *D
Page 2 of 9


Part Number Z9973
Description Multi-Output Zero Delay Buffer
Maker Cypress Semiconductor
Total Page 9 Pages
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