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DM9161 Datasheet Preview

DM9161 Datasheet

10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER

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DM9161
10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver
1. General Description
The DM9161 is a physical layer, single-chip, and low
power transceiver for 100BASE-TX 100BASE-FX and
10BASE-T operations. On the media side, it provides
a direct interface either to Unshielded Twisted Pair
Category 5 Cable (UTP5) for 100BASE-TX Fast
Ethernet, or UTP5/UTP3 Cable for 10BASE-T
Ethernet. Through the Media Independent Interface
(MII), the DM9161 connects to the Medium Access
Control (MAC) layer, ensuring a high inter-operability
from different vendors.
The DM9161 uses a low power and high performance
CMOS process. It contains the entire physical layer
functions of 100BASE-TX as defined by IEEE802.3u,
including the Physical Coding Sublayer (PCS),
Physical Medium Attachment (PMA), Twisted Pair
Physical Medium Dependent Sublayer (TP-PMD),
10BASE-TX Encoder/Decoder (ENC/DEC), and
Twisted Pair Media Access Unit (TPMAU). The
DM9161 provides a strong support for the
auto-negotiation function, utilizing automatic media
speed and protocol selection. Furthermore, due to the
built-in wave-shaping filter, the DM9161 needs no
external filter to transport signals to the media in
100BASE-TX or 10BASE-T Ethernet operation.
2. Block Diagram
100Base-FX
PECL
Interface
100Base-TX
Transceiver
Clock
Circuit
Block
100Base-
TX
PCS
MII/RMII/
GPSI
Interface
10Base-T
TX/RX Module
Auto-Negotiation
Biasing/
Power
Block
MII
Register
LED Driver
MII
Management
Control
Final
Version: DM9161-DS-F05
September 10, 2008
1




DAVICOM

DM9161 Datasheet Preview

DM9161 Datasheet

10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER

No Preview Available !

DM9161
10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver
Table of Contents
1. General Description.............................................. 3
2. Block Diagram ...................................................... 3
3. Features ............................................................... 4
4. Pin Configuration: DM9161 LQFP........................ 5
5. Pin Description ..................................................... 6
5.1 Normal MII Interface, 21 pins ............................. 6
5.2 Media Interface, 4 pins ....................................... 8
5.3 LED Interface, 3 pins.......................................... 8
5.4 Mode, 2 pins....................................................... 8
5.5 Bias and Clock, 4 pins........................................ 9
5.6 Power, 13 pins.................................................... 9
5.7 Table A ............................................................... 9
5.8 Pin Maps of Normal MII, Reduced MII, and
10Base-T GPSI (7-Wired) Mode..................... 10
6. LED Configuration .............................................. 11
7. Functional Description........................................ 12
7.1 MII interface...................................................... 12
7.2 100Base-TX Operation..................................... 14
7.2.1 100Base-TX Transmit ................................... 14
7.2.1.1 4B5B Encoder ............................................ 15
7.2.1.2 Scrambler .................................................. .15
7.2.1.3 Parallel to Serial Converter ........................ 15
7.2.1.4 NRZ to NRZI Encoder ................................ 15
7.2.1.5 MLT-3 Converter ........................................ 15
7.2.1.6 MLT-3 Driver .............................................. 15
7.2.1.7 4B5B Code Group ...................................... 16
7.2.2 100Base-TX Receiver ................................... 17
7.2.2.1 Signal Detect .............................................. 17
7.2.2.2 Adaptive Equalizer ..................................... 17
7.2.2.3 MLT-3 to NRZI Decoder ............................. 17
7.2.2.4 Clock Recovery Module ............................. 18
7.2.2.5 NRZI to NRZ............................................... 18
7.2.2.6 Serial to Parallel ......................................... 18
7.2.2.7 Descrambler ............................................... 18
7.2.2.8 Code Group Alignment............................... 18
7.2.2.9 4B5B Decoder ............................................ 18
7.2.3 10Base-T Operation ...................................... 18
7.2.4 Collision Detection......................................... 18
7.2.5 Carrier Sense ................................................ 18
7.2.6 Auto-Negotiation............................................ 18
7.2.7 MII Serial Management ................................. 19
7.2.8 Serial Management Interface ........................ 19
7.2.9 Management Interface – Read Frame
Structure ......................................................... 19
7.2.10 Management Interface – Write Frame Structure
...................................................................... 19
7.2.11 Power Reduced Mode................................. 20
7.2.12 Power Down Mode ...................................... 20
2
7.2.13 Reduced Transmit Power Mode.................. 20
8. MII Register Description ..................................... 21
8.1 Basic Mode Control Register (BMCR) - 00 ...... 22
8.2 Basic Mode Status Register (BMSR) - 01........ 23
8.3 PHY ID Identifier Register #1 (PHYIDR1) - 02. 24
8.4 PHY ID Identifier Register #2 (PHYIDR2) - 03. 24
8.5 Auto-negotiation Advertisement Register (ANAR)
- 04 ................................................................... 25
8.6 Auto-negotiation Link Partner Ability Register
(ANLPAR) - 05 ................................................. 26
8.7 Auto-negotiation Expansion Register (ANER)
- 06 ................................................................... 27
8.8 DAVICOM Specified Configuration Register
(DSCR) –16 ......................................................27
8.9 DAVICOM Specified Configuration and Status
Register (DSCSR) - 17 .................................... 29
8.10 10Base-T Configuration / Status (10BTCSR) - 18
......................................................................... 30
8.11 DAVICOM Specified Interrupt Register - 21... 30
8.12 DAVICOM Specified Receive Error Counter
Register (RECR) - 22....................................... 31
8.13 DAVICOM Specified Disconnect Counter
Register (DISCR) - 23...................................... 31
8.14 DAVICOM Hardware Reset Latch State
Register (RLSR) - 24....................................... 31
9. DC and AC Electrical Characteristics
9.1 Absolute Maximum Ratings( 25°C ) .................. 32
9.2 Operating Conditions........................................ 32
9.3 DC Electrical Characteristics............................ 33
9.4 AC Electrical Characteristics & Timing
Waveform .......................................................... 33
9.4.1 TP Interface ................................................... 33
9.4.2 Oscillator/Crystal Timing ............................... 33
9.4.3 MDC/MDIO Timing ........................................ 34
9.4.4 MDIO Timing when OUTPUT by STA........... 34
9.4.5 MDIO Timing when OUTPUT by DM9161 .... 34
9.4.6 100Base-TX Transmit Timing Parameters.... 35
9.4.7 100Base-TX Transmit Timing Diagram......... 35
9.4.8 100Base-TX Receive Timing Parameters..... 35
9.4.9 MII 100Base-TX Receive Timing Diagram.... 36
9.4.10 MII 10Base-T Nibble Transmit Timing
Parameters.................................................. 36
9.4.11 MII 10Base-T Nibble Transmit Timing
Diagram ....................................................... 36
9.4.12 MII 10Base-T Receive Nibble Timing
Parameters.................................................. 37
9.4.13 MII 10Base-T Receive Nibble Timing
Diagram ....................................................... 37
Final
Version: DM9161-DS-F05
September 10, 2008


Part Number DM9161
Description 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
Maker DAVICOM
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DM9161 Datasheet PDF






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