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DM9161C Datasheet Preview

DM9161C Datasheet

10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver

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DM9161C
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
DAVICOM Semiconductor, Inc.
DM9161C
10/100 Mbps Fast Ethernet
Physical Layer Single Chip Transceiver
DATA SHEET
Final
Version: DM9161C-DS-F01
August 31, 2012
1 Final
Version: DM9161C-DS-F01
August 31, 2012




DAVICOM

DM9161C Datasheet Preview

DM9161C Datasheet

10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver

No Preview Available !

DM9161C
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Content
1. GENERAL DESCRIPTION.................................................................................................................................................................. 4
2. FEATURES ............................................................................................................................................................................................ 4
3. BLOCK DIAGRAM ............................................................................................................................................................................... 5
4. PIN CONFIGURATION: ....................................................................................................................................................................... 6
4.1 48-PIN LQFP...................................................................................................................................................................................... 6
5. PIN DESCRIPTION............................................................................................................................................................................... 7
5.1 NORMAL MII INTERFACE .................................................................................................................................................................... 7
5.2 MEDIA INTERFACE .............................................................................................................................................................................. 9
5.3 LED INTERFACE................................................................................................................................................................................. 9
5.4 MODE.................................................................................................................................................................................................. 9
5.5 BIAS AND CLOCK ..............................................................................................................................................................................11
5.6 POWER.............................................................................................................................................................................................11
5.7 TABLE A (MEDIA TYPE SELECTION)..................................................................................................................................................11
5.8 PIN MAPS OF NORMAL MII, REDUCED MII, AND 10BASE-T GPSI (7-WIRED) MODE.....................................................................11
6. LED CONFIGURATION.....................................................................................................................................................................13
6.1 LED FUNCTION DESCRIPTION .........................................................................................................................................................14
7. FUNCTIONAL DESCRIPTION .........................................................................................................................................................15
7.1 MII INTERFACE..................................................................................................................................................................................15
7.2 100BASE-TX OPERATION................................................................................................................................................................18
8. MII REGISTER DESCRIPTION.........................................................................................................................................................25
8.1 BASIC MODE CONTROL REGISTER (BMCR) - 00............................................................................................................................26
8.2 BASIC MODE STATUS REGISTER (BMSR) - 01...............................................................................................................................27
8.3 PHY ID IDENTIFIER REGISTER #1 (PHYID1) - 02...........................................................................................................................28
8.4 PHY ID IDENTIFIER REGISTER #2 (PHYID2) - 03...........................................................................................................................28
8.5 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) - 04......................................................................................................29
8.6 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR) – 05.......................................................................................30
8.7 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) - 06 ..............................................................................................................31
8.8 DAVICOM SPECIFIED CONFIGURATION REGISTER (DSCR) - 16..................................................................................................31
8.9 DAVICOM SPECIFIED CONFIGURATION AND STATUS REGISTER (DSCSR) - 17 .........................................................................33
8.10 10BASE-T CONFIGURATION/STATUS (10BTCSR) - 18..............................................................................................................34
8.12 (SPECIFIED CONFIG) REGISTER – 20 .............................................................................................................................................35
8.13 DAVICOM SPECIFIED INTERRUPT REGISTER – 21......................................................................................................................36
8.14 DAVICOM SPECIFIED RECEIVE ERROR COUNTER REGISTER (RECR) – 22.............................................................................36
8.15 DAVICOM SPECIFIED DISCONNECT COUNTER REGISTER (DISCR) – 23..................................................................................37
8.16 DAVICOM HARDWARE RESET LATCH STATE REGISTER (RLSR) – 24......................................................................................38
8.17 POWER SAVING CONTROL REGISTER (PSCR) – 29 ....................................................................................................................38
9. DC AND AC ELECTRICAL CHARACTERISTICS .......................................................................................................................39
9.1 ABSOLUTE MAXIMUM RATINGS (25°C)............................................................................................................................................39
9.2 OPERATING CONDITIONS .................................................................................................................................................................39
9.3 DC ELECTRICAL CHARACTERISTICS (DVDD = 3.3V) .....................................................................................................................40
2 Final
Version: DM9161C-DS-F01
August 31, 2012


Part Number DM9161C
Description 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Maker DAVICOM
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DM9161C Datasheet PDF






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