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DM9163 Datasheet Preview

DM9163 Datasheet

10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver

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DM9163
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
DAVICOM Semiconductor, Inc.
DM9163
10/100 Mbps Fast Ethernet Physical Layer Single
Chip Transceiver
DATA SHEET
Doc No: DM9163-16-MCO-DS-P01
August 20, 2014
Version: DM9163-16-MCO-DS-P01
August 20, 2014
1




DAVICOM

DM9163 Datasheet Preview

DM9163 Datasheet

10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver

No Preview Available !

DM9163
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Content
1 General Description........................................................................................................................... 4
2 Features ............................................................................................................................................. 5
3 Block Diagram ................................................................................................................................... 6
4 Pin Configuration .............................................................................................................................. 7
4.1 48-Pin LQFP.................................................................................................................................. 7
5 Pin Description .................................................................................................................................. 8
5.1 Normal MII Interface ...................................................................................................................... 8
5.2 Media Interface.............................................................................................................................10
5.3 LED Interface................................................................................................................................10
5.4 Mode ............................................................................................................................................10
5.5 Bias and Clock..............................................................................................................................11
5.6 Power ...........................................................................................................................................11
5.8 Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI (7-Wired) Mode.................................12
6 LED Configuration............................................................................................................................13
6.1 LED Function Description .............................................................................................................14
6.1.1 Dual-LED Application Circuit..............................................................................................14
7 Function Description........................................................................................................................15
7.1 MII Interface .................................................................................................................................16
7.2 100Base –TX Operation................................................................................................................17
7.2.1 100Base-TX Transmit ........................................................................................................17
7.2.2 100Base-TX Receiver........................................................................................................21
7.2.2.5 NRZI to NRZ ...................................................................................................................................21
7.2.2.6 Serial to Parallel ..............................................................................................................................22
7.2.2.7 Descrambler....................................................................................................................................22
7.2.2.8 Code Group Alignment ....................................................................................................................22
7.2.2.9 4B5B Decoder.................................................................................................................................22
7.2.3 10Base-T Operation ..........................................................................................................22
7.2.4 Collision Detection.............................................................................................................22
7.2.5 Carrier Sense ....................................................................................................................22
7.2.6 Auto-Negotiation................................................................................................................23
7.2.7 MII Serial Management......................................................................................................23
7.2.8 Serial Management Interface.............................................................................................23
7.2.9 Management Interface - Read Frame Structure .................................................................23
7.2.10 Management Interface - Write Frame Structure................................................................23
7.2.11 Power Reduced Mode .....................................................................................................24
7.2.12 Power Down Mode ..........................................................................................................24
7.2.13 Reduced Transmit Power Mode .......................................................................................24
7.3 HP Auto-MDIX Functional Descriptions .........................................................................................25
8 MII Register Description...................................................................................................................26
8.1 Basic Mode Control Register (BMCR) - 00 ....................................................................................27
8.2 Basic Mode Status Register (BMSR) – 01.....................................................................................28
8.3 PHY ID Identifier Register #1 (PHYID1) - 02 .................................................................................29
8.4 PHY ID Identifier Register #2 (PHYID2) - 03 .................................................................................29
8.5 Auto-Negotiation Advertisement Register (ANAR) – 04 .................................................................30
8.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) – 05.......................................................31
8.7 Auto-Negotiation Expansion Register (ANER) – 06 .......................................................................32
8.8 DAVICOM Specified Configuration Register (DSCR) - 16 ..............................................................32
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 17 .........................................34
8.10 10BASE-T Configuration/Status (10BTCSR) – 18 .......................................................................35
8.11 Power down Control Register (PWDOR) – 19...................................................................................35
8.12 (Specified Config) Register – 20..................................................................................................36
8.13 DAVICOM Specified Interrupt Register – 21 ................................................................................37
8.14 DAVICOM Specified Receive Error Counter Register (RECR) – 22 .............................................38
8.15 DAVICOM Specified Disconnect Counter Register (DISCR) – 23 ................................................38
8.16 DAVICOM Hardware Reset Latch State Register (RLSR) – 24 ....................................................38
8.17 Cable Control Register (CABCR) – 28 .........................................................................................39
8.18 Power Saving Control Register (PSCR) – 29......................................................................................39
Doc No: DM9163-16-MCO-DS-P01
August 20, 2014
2


Part Number DM9163
Description 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Maker DAVICOM
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DM9163 Datasheet PDF






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