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DM9331A Datasheet Preview

DM9331A Datasheet

100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip

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DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
1. General Description
The DM9331A is a physical-layer, single-chip, low
power transceiver for media converter application. On
the media side, it provides a direct interface either to
Unshielded Twisted Pair Category 5 Cable (UTP5)
for 100BASE-TX Fast Ethernet, and it also provides
PECL interface to connect the external fiber optical
transceiver. Through the Media Converter Interface
(MCI), the DM9331A connects to another DM9331A
for the twisted pair to the fiber media converter, or
fiber to fiber repeater.
The DM9331A uses a low-power and
high-performance CMOS process. It contains the
entire physical layer functions of 100BASE-TX as
defined by IEEE802.3u, including the Physical
Coding Sublayer (PCS), Physical Medium
Attachment (PMA), Twisted Pair Physical Medium
Dependent Sublayer (TP-PMD) and a PECL
compliant interface for a fiber optical module,
compliant with ANSI X3.166. The DM9331A provides
a strong support for the auto-negotiation function,
utilizing automatic selection of full or half-duplex
mode. Furthermore, due to the built-in wave-shaping
filter, the DM9331A needs no external filter to
transport signals to the media on the 100base-TX
Ethernet operation.
2. Block Diagram
100Base-FX
PECL
Interface
100Base-TX
Transceiver
Clock
Circuit
Block
100Base-
TX
PCS
Media
Converter
Interface
Auto-Negotiation
TX/RX Module
Biasing/
Power
Block
MII
Register
LED Driver
MII
Management
Control
Preliminary
Version: DM9331A-DS-P02
October 7, 2008
1




DAVICOM

DM9331A Datasheet Preview

DM9331A Datasheet

100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip

No Preview Available !

DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
Table of Contents
1. General Description.............................................. 1
2. Block Diagram ...................................................... 1
3. Features ............................................................... 4
4. Pin Configuration: DM9331A LQFP ..................... 5
5. Pin Description ..................................................... 6
5.1 Media Converter Interface, 19 pins .................... 6
5.2 Media Interface, 5 pins ....................................... 7
5.3 LED Interface, 3 pins.......................................... 7
5.4 Mode, 1 pin......................................................... 8
5.5 Bias and Clock, 3 pins........................................ 8
5.6 Power, 15 pins.................................................... 8
5.7 Table A ............................................................... 9
6.LED Configuration ............................................... 10
7. Functional Description........................................ 11
7.1 MCI interface .................................................... 11
7.2 100Base-TX Operation ................. …………….12
7.2.1 100Base-TX Transmit ................................... 12
7.2.1.1 4B5B Encoder ............................................ 13
7.2.1.2 Scrambler ................................................... 13
7.2.1.3 Parallel to Serial Converter ........................ 13
7.2.1.4 NRZ to NRZI Encoder ................................ 13
7.2.1.5 NRZI to MLT-3............................................ 13
7.2.1.6 MLT-3 Driver .............................................. 13
7.2.1.7 4B5B Code Group ...................................... 15
7.2.2 100Base-TX Receiver ................................... 15
7.2.2.1 Signal Detect .............................................. 15
7.2.2.2 Adaptive Equalizer ..................................... 15
7.2.2.3 MLT-3 to NRZI Decoder............................. 15
7.2.2.4 Clock Recovery Module ............................. 15
7.2.2.5 NRZI to NRZ............................................... 15
7.2.2.6 Serial to Parallel ......................................... 15
7.2.2.7 Descrambler ............................................... 15
7.2.2.8 Code Group Alignment............................... 15
7.2.2.9 4B5B Decoder ............................................ 16
7.2.3 Auto-Negotiation............................................ 16
7.2.4 MII Serial Management ................................. 16
7.2.4.1 Serial Management Interface ..................... 16
7.2.4.2 Management Interface – Read Frame
Structure………........................................ 16
7.2.4.3 Management Interface – Write Frame
Structure ................................................. 17
7.2.5 Power Reduced Mode................................... 17
7.2.6 Power Down Mode ........................................ 17
7.2.7 Reduced Transmit Power Mode.................... 17
7.2.8 Link Fault Propagation .................................. 17
2
7.2.9 Remote Auto-loopback
Diagnostic………..…..17
8. MII Register Description..................................... 18
8.1 Basic Mode Control Register (BMCR) - 00...... 19
8.2 Basic Mode Status Register (BMSR) - 01 ....... 20
8.3 Auto-negotiation Advertisement Register (ANAR)
- 04 .................................................................. 21
8.4 Auto-negotiation Link Partner Ability Register
(ANLPAR) - 05 ................................................ 22
8.5 Auto-negotiation Expansion Register (ANER)
- 06 .................................................................. 22
8.6 DAVICOM Specified Configuration Register
(DSCR)-16 …………………………………...……2
3
8.7 DAVICOM Specified Configuration and Status
Register (DSCSR) - 17 ................................... 24
8.8 DAVICOM Specified Interrupt Register - 21 .... 25
9. DC and AC Electrical Characteristics……………26
9.1 Absolute Maximum Ratings ............................. 26
9.2 Operating Conditions ....................................... 26
9.3 DC Electrical Characteristics ........................... 27
9.4 AC Electrical Characteristics & Timing
Waveforms...................................................... 28
9.4.1 TP Interface................................................... 28
9.4.2 Oscillator Timing ........................................... 28
9.4.3 MDC/MDIO Timing........................................ 28
9.4.4 MDIO Timing when OUTPUT by STA .......... 28
9.4.5 MDIO Timing when OUTPUT by DM9331A . 29
9.4.6 Auto-negotiation and Fast Link Pulse Timing
Parameters .................................................. 29
9.4.7 Auto-negotiation and Fast Link Pulse Timing
Diagram ....................................................... 29
9.4.8 TXD to TP or FX Transmit Latency Timing
Diagram ....................................................... 30
9.4.9 TXD to TP or FX Transmit Latency Parameters
..................................................................... 30
9.4.10 TP or FX to RXD Receive Latency Timing
Diagram ....................................................... 30
9.4.11 TP or FX to RXD Receive Latency Parameters
.................................................................... 30
10. Application Notes ............................................. 31
10.1 Network Interface Signal Routing .................. 31
10.2 100Base-TX Side Application ........................ 31
10.3 100Base-TX Side (Power Reduction
Application) .................................................. 32
10.4 100Base-FX Side Application ........................ 33
10.5 Power Decoupling Capacitors ....................... 34
10.6 Ground Plane Layout ..................................... 35
Preliminary
Version: DM9331A-DS-P02
October 20, 2008


Part Number DM9331A
Description 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
Maker DAVICOM
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