The DS1384 watchdog timekeeping controller is a self-contained real-time clock, alarm, watchdog timer,
and interval timer that provides control of up to 128k x 8 of external low-power CMOS static RAM in a
44-pin quad flat-pack package. An external crystal and battery are the only components required to
maintain time of day and RAM memory contents in the absence of power. Access to all RTC functions
and the external RAM is the same as conventional bytewide SRAM. Data is maintained in the watchdog
timekeeper by intelligent control circuitry, which detects the status of VCC and write protects both
memory and timekeeping functions when VCC is out of tolerance. Timekeeper information includes
hundredths of seconds, seconds, minutes, hours, day, date, month, and year. The date at the end of the
month is automatically adjusted for months with fewer than 31 days, including correction for leap year.
The timekeeper operates in either 12- or 24-hour format with an AM/PM indicator. The watchdog internal
timer provides watchdog alarm windows and interval timing between 0.01 seconds and 99.99 seconds.
The real time alarm provides for preset times of up to one week. All the RTC functions and the internal
50 bytes of RAM reside in the lower 64 bytes of the attached RAM memory map. The externally attached
static RAM is controlled by the DS1384 via the OER and CEO signals.
Automatic backup and write protection for an external SRAM is provided through the VCCO, CEO, and
OER pins. The lithium energy source used to permanently power the real time clock is also used to retain
RAM data in the absence of VCC power through the VCCO pin. The chip enable output to RAM (CEO) and
the output enable to RAM (OER) are controlled during power transients to prevent data corruption. The
DS1384 is a complete one-chip solution in that an external crystal and battery are the only components
required to maintain time of day memory status in the absence of power.
Interrupt Output B (Active High or Low). INTB outputs the alarm
(time of day or watchdog) that is not selected for INTA. This pin is
programmable high or low. Both INTA and INTB/(INTB) are open-
drain outputs. The two interrupts and the internal clock continue to run
regardless of the VCC level. However, it is important to ensure that the
pullup resistors used with the interrupt pins are never pulled up to a
value that is greater than VCC + 0.3V. As VCC falls below
approximately 3.0V, a power-switching circuit turns the lithium
energy source on to maintain the clock and timer data functionality. It
is also required to ensure that during this time (battery-backup mode)
the voltage present at INTA and INTB/(INTB) never exceeds VBAT.
At all times the current on each should not exceed +2.1mA or -1.0mA.
Address Bus (Input). The address bus inputs qualified by CE, OE,
WE, and VCC are used to select the on-chip 64 timekeeping/RAM
registers within the memory map of the external SRAM controlled as
nonvolatile storage. When the qualified address bus value is within the
range of 00000H–0003FH, one of the internal registers is selected and
OER remains inactive. When the value is outside the range, OE is
passed through to OER.
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