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ADC-HX12BMC Datasheet Preview

ADC-HX12BMC Datasheet

8 and 20u sec Analog-to-Digital Converters

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®®
ADC-HX, ADC-HZ Series
12-Bit, 8 and 20μsec Analog-to-Digital Converters
FEATURES
12-bit resolution
8 or 20 microsecond conversion times
5 input voltage ranges
Internal high Z input buffer
Short-cycle operation
MIL-STD-883 models available
+15V POWER
28
–15V POWER
31
PRODUCT OVERVIEW
The ADC-HX and ADC-HZ Series are self-
Both models have identical operation except for
contained, high-performance, 12-bit A/D convert- conversion speed. They can be short-cycled to give
ers manufactured with thick and thin-film hybrid faster conversions in lower-resolution applica-
technology. They use the successive approximation tions. Use of the internal buffer amplifier increases
conversion technique to achieve a 12-bit conver- conversion time by 3 microseconds, the settling
sion in 20 and 8 microseconds, respectively. Five time of the amplifier. Output coding is comple-
input voltage ranges are programmable by external mentary binary, complementary offset binary, or
pin connection. An internal buffer amplifier is also complementary two’s complement. Serial data is
provided for applications in which 50 megohm
also brought out. The package is a 32-pin ceramic
input impedance is required.
TDIP. Models are available for use in commercial
These converters utilize a fast 12-bit monolithic (0 to +70°C), industrial (–40 to +100°C), or military
DAC which includes a precision zener reference
(–55 to +125°C) operating temperature ranges.
source. The circuit also contains a fast mono-
MIL-STD-883 and DESC Standard Military Drawing
lithic comparator, a monolithic 12-bit successive models are also available.
approximation register, a clock and a monolithic
buffer amplifier. Nonlinearity is specified at
±1/2LSB maximum.
INPUT/OUTPUT CONNECTIONS
Pin Function Pin Function
1 BIT 12 (LSB)
32 SERIAL DATA OUTPUT
2 BIT 11
31 –15V POWER
3 BIT 10
30 BUFFER INPUT
4 BIT 9
29 BUFFER OUTPUT
5 BIT 8
28 +15V POWER
6 BIT 7
27 GAIN ADJUST
7 BIT 6
26 ANALOG COMMON
8 BIT 5
25 20V INPUT RANGE
9 BIT 4
24 10V INPUT RANGE
10 BIT 3
23 BIPOLAR OFFSET
11 BIT 2
22 COMPARATOR INPUT
12 BIT 1 (MSB)
21 START CONVERT
13 BIT 1 (MSB)
20 E.O.C. (STATUS)
14 SHORT CYCLE
19 CLOCK OUT
REF. OUT
18
+5V POWER
16
15 DIGITAL COMMON
16 +5V POWER
18 REFERENCE OUT
17 CLOCK RATE
BUFFER
INPUT
30
BUFFER 29
OUTPUT
BIPOLAR
OFFSET
23
COMPARATOR 22
INPUT
10V
INPUT
24
20V
INPUT
25
ANALOG
COMMON
26
BUFFER
+ AMPLIFIER
6.3kW
5kW COMPARATOR
5kW
CLOCK
PRECISION
REF (+6.3V)
12-BIT DAC
SUCCESSIVE
APPROXIMATION
REGISTER
GAIN
27 ADJUST
15
DIGITAL
COMMON
14 SHORT
CYCLE
20
E.O.C.
STATUS
17
CLOCK
RATE
19 21 1 2 3 4 5 6 7 8 9 10 11 12 13
CLOCK START 12 11 10 9 8 7 6 5 4 3 2 1 1
OUT CONV. LSB.
BIT NO.
MSB MSB
PARALLEL DATA OUT
Figure 1. Functional Block Diagram
32
SERIAL
DATA
OUT
DATEL
• 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
ADC-HXHZ.C01 Page 1 of 7




Datel

ADC-HX12BMC Datasheet Preview

ADC-HX12BMC Datasheet

8 and 20u sec Analog-to-Digital Converters

No Preview Available !

®®
ADC-HX, ADC-HZ Series
12-Bit, 8 and 20μsec Analog-to-Digital Converters
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
+15V Supply, Pin 28
–15V Supply, Pin 31
+5V Supply, Pin 16
Digital Inputs, Pins 14, 21
Analog Inputs, Pins 24, 25
Buffer Input, Pin 30
Lead Temperature (10 seconds)
LIMITS
+18
–18
+7
±5.5
±25
±15
300
UNITS
Volts
Volts
Volts
Volts
Volts
Volts
°C
Functional Specifications
(Typical at +25°C and ±15V and +5V supplies unless otherwise noted)
INPUTS
ADC-HX12B
ADC-HZ12B
Analog Input Ranges
Unipolar
Bipolar
Input Impedance
Input Impedance with Buffer
Input Bias Current of Buffer
Start Conversion
0 to +5V, 0 to +10V
±2.5V, ±5V, ±10V
2.5k (0 to +5V, ±2.5V)
5k (0 to +10V, ±5V)
10k (±10V)
50 megohms
125nA typical, 250nA max.
+2V min. to +5.5V max. positive pulse with dur-
ation of 100ns min. Rise and fall times <30ns.
Logic "1" to "0" transition resets converter and
initiates next conversion. Loading: 2 TTL loads.
PERFORMANCE
Resolution
Nonlinearity
Differential Nonlinearity
Accuracy Error
Gain (before adjustment)
Zero, Unipolar (before adj.)
Offset, Bipolar (before adj.)
Temperature Coefficient
Gain
Zero, Unipolar
Offset, Bipolar
Diff. Nonlinearity Tempco
No Missing Codes
Conversion Time
12 Bits
10 Bits
8 Bits
Buffer Settling Time (10V step)
Power Supply Rejection
12 bits
±1/2LSB max.
±3/4LSB max.
±0.2%
±0.1% of FSR
±0.2% of FSR
±20ppm/°C max.
±5ppm/°C of FSR max.
±10ppm/°C of FSR max.
±2ppm/°C of FSR max.
Over opererating temperature range
20μs max.
15μs max.
10μs max.
3μs to ±0.01%
±0.004%/% supply max.
8μs max.
6μs max.
4μs max.
OUTPUTS
Parallel Output Data
Unipolar Coding
Bipolar Coding
Serial Output Data
End of Conversion (Status)
Clock Output
Internal Reference
Reference Tempco
External Reference Current
12 parallel lines of data held until next
conversion command.
VOUT ("0") +0.4V
VOUT ("1") +2.4V
Complementary binary
Complementary offset binary
Complementary two’s complement
NRZ successive decision pulses out, MSB first.
Compl. binary or compl. offset binary coding.
Conversion status signal. Output is logic "1"
during reset and conversion and logic "0"
when conversion complete.
Train of positive going +5V 100ns pulses.
600kHz for ADC-HX and 1.5MHz for
ADC-HZ (pin 17 grounded).
+6.3V
±20ppm/°C max.
2.5mA max.
POWER REQUIREMENTS
Power Supply Voltages
+15V ±0.5V at +20mA
–15V ±0.5V at –25mA
+5V ±0.25V at +85mA
PHYSICAL/ENVIRONMENTAL
Operating Temp. Range, Case
Storage Temperature Range
Package Type
Weight
Thermal Impedance
θJC
θJA
0 to +70°C, –40 to +100°C, –55 to +125°C
–65 to +150°C
32-pin ceramic TDIP
0.5 ounces (14 grams)
6°C/W
30°C/W
Footnotes:
Adjustable to zero.
FSR is full scale range and is 10V for 0 to +10V or ±5V inputs and 20V for
±10V input, etc.
Without buffer amplifier used. ADC-HZ may require external adjustment
of clock rate.
Short cycled operation.
All digital outputs can drive 2 TTL loads.
TECHNICAL NOTES
1. It is recommended that the ±15V power input pins both be bypassed to ground with a 0.01μF ceramic
capacitor in parallel with a 1μF electrolytic capacitor and the +5V power input pin be bypassed to ground
with a 10μF electrolytic capacitor as shown in the connection diagrams. In addition, GAIN ADJUST (pin 27)
should be bypassed to ground with a 0.01μF ceramic capacitor. These precautions will assure noise free
operation of the converter.
2. DIGITAL COMMON (pin 15) and ANALOG COMMON (pin 26) are not connected together internally, and
therefore must be connected as directly as possible externally. It is recommended that a ground plane be
run underneath the case between the two commons. Analog ground and ±15V power ground should be
run to pin 26 whereas digital ground and +5V ground should be run to pin 15.
3. External adjustment of zero or offset and gain are made by using trimming potentiometers connected as
shown in the connection diagrams. The potentiometer values can be between 10k and 100k Ohms and
should be 100ppm/°C cermet types. The trimming pots should be located as close as possible to the con-
verter to avoid noise pickup. In some cases, for example 8-bit short-cycled operation, external adjustment
may not be necessary.
4. Short-cycled operation results in shorter conversion times when the conversion is truncated to less than
12 bits. This is done by connecting SHORT CYCLE (pin 14) to the output bit following the last bit desired.
For example, for an 8-bit conversion, pin 14 is connected to the bit 9 output. Maximum conversion times
are given for short-cycled conversions of 8 or 10 bits. In these two cases, the clock rate is accelerated by
connecting the CLOCK RATE adjust (pin 17) to +5V (10 bits) or +15V (8 bits). The clock rate should not be
arbitrarily speeded up to exceed the maximum conversion rate at a given resolution, as missing codes will
result.
5. Note that output coding is complementary coding. For unipolar operation it is complementary binary, and
for bipolar operation it is complementary offset binary or complementary two’s complement. In cases in
which bipolar coding of offset binary or two’s complement is required, this can be achieved by inverting the
analog input to the converter (using an op amp connected for gain of –1). The converter is then calibrated
so that –FS analog input gives an output code of 0000 0000 0000, and +FS – 1LSB gives 1111 1111 1111.
6. These converters can be operated with an external clock. To accomplish this, a negative pulse train is
applied to START CONVERT (pin 21). The rate of the external clock must be lower than the rate of the
internal clock as adjusted (see Short Cycle Operation tables) for the converter resolution selected. The
pulse width of the external clock should be between 100 and 300 nanoseconds. Each N-bit conversion
cycle requires a pulse train of N + 1 clock pulses for completion, e.g., an 8-bit conversion requires 9 clock
pulses for completion. A continuous pulse train may be used for consecutive conversions, resulting in an
N-bit conversion every N + 1 pulses, or the E.O.C. output may be used to gate a continuous pulse train for
single conversions.
7. When the input buffer amplifier is used, a delay equal to its settling time must be allowed between the input
level change, such as a multiplexer channel change, and the negative-going edge of the START CONVERT
pulse. If the buffer is not required, BUFFER INPUT (pin 30) should be tied to ANALOG COMMON (pin 26). This
prevents the unused amplifier from introducing noise into the converter. For applications not using the buffer,
the converter must be driven from a source with an extremely low output impedance.
DATEL
• 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
ADC-HXHZ.C01 Page 2 of 7


Part Number ADC-HX12BMC
Description 8 and 20u sec Analog-to-Digital Converters
Maker Datel
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