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DM9801A Datasheet Preview

DM9801A Datasheet

1M Home Phoneline Network Physical Layer Single Chip Transceiver

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DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
General Description
The DM9801A is a physical-layer, single-chip, low-power
transceiver for 1M Home Phoneline Network applications.
On the media side, it provides an interface to a Home
Phoneline wiring system. The reconciliation layer interfaces
to the DM9801A either through an IEEE802.3u subset
Media Independent Interface (MII) or a pseudo-standard
General Purpose Serial Interface (GPSI). A management
interface is provided by MDIO/MDC when operating in MII
mode, or a Serial Peripheral Interface bus when operating in
GPSI mode.
The DM9801A uses a low-power and high-performance
CMOS process. It contains the entire physical layer
functions of 1M as defined by Home Phoneline Network
Alliance, Rev. 1.1, including the Physical Coding Sublayer,
(RLL25) Encoder/Decoder (ENC/DEC), 4-wire HN Driver
circuit and receiver analog front end (AFE).
Patent-Pending Circuitry Includes:
Enhanced 4-wire Home Network transceiver circuit.
Compatible with HomePNA 1M PHY specification version
1.1 and HomePNA certification document version 1.0
Block Diagram
GPSI - MII
Transmit
GPSI - MII
Receive
Muxed
GPSI
or Mii
Interface
RLL25
Encoder
Master
PHY
Controller
Transmit
Timing
Generator
HN
Secondary
Driver
HNB+/-
HN
Primary
Driver
HNA+/-
Interface
Select
RLL25
Decoder
Receiever
and
Digital PLL
Receiver
AFE
Final
Version: DM9801A-DS-F01
May 30, 2001
1




Davicom

DM9801A Datasheet Preview

DM9801A Datasheet

1M Home Phoneline Network Physical Layer Single Chip Transceiver

No Preview Available !

DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Features
1M Home Phoneline Network physical-layer, single-
chip transceiver
Compatible with HomePNA 1M PHY specification
version 1.1 and HomePNA certification document
version 1.0
Supports the MII including the MDIO/MDC serial
management interface
Supports the GPSI including a SPI serial
management interface
Supports Link Integrity function
Smart equalizer circuit for 1M receiver
Supports Patent Pending 4-wire operation
Supports hardware or software speed select
Supports Interrupt on change, eliminates
management polling
Flexible built-in LED support for TX Activity, RX
Activity and Collision Indication or Activity, Link state
and Collision
Digital PLL circuit using advanced digital algorithm to
reduce jitter
Low-power, high-performance CMOS process
Available in a small outline 100-pin LQFP
3.3V DC power with 5V DC tolerant I/O
2 Final
Version: DM9801A-DS-F01
May 30, 2001


Part Number DM9801A
Description 1M Home Phoneline Network Physical Layer Single Chip Transceiver
Maker Davicom
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