P3P4GF4BLF - 4G Bits Die DDRIII SDRAM

Datasheet Details

Part number	P3P4GF4BLF
Manufacturer	Deutron Electronics
File Size	2.19 MB
Description	4G Bits Die DDRIII SDRAM
Datasheet	P3P4GF4BLF-DeutronElectronics.pdf

Double-data-rate architecture: two data transfers per clock cycle.
The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transitions.
Commands ent.

📁 P3P4GF4BLF Similar Datasheet

Other Datasheets by Deutron Electronics

Published: Jun 19, 2014 |