* Double-data-rate architecture: two data transfers per clock cycle
* The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
P3P4GF4BLF Datasheet (2.19 MB)
P3P4GF4BLF
Deutron Electronics
2.19 MB
4g bits die ddriii sdram.
4G B Die DDRIII SDRAM Specification P3P4GF4BLF Deutron Electronics Corp. 8F, 68, Sec. 3, NanKing E. RD., Taipei 104, Taiwan, R.O.C. TEL: (886)-2-251.
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