P3P4GF4BLF Description
4G B Die DDRIII SDRAM Specification P3P4GF4BLF Deutron Electronics Corp. RD., Taipei 104, Taiwan, R.O.C. (886)-2-2517-4575 P3P4GF4BLF (256M words x 16 bits) Specifications Density:.
P3P4GF4BLF Key Features
- Double-data-rate architecture: two data transfers per clock cycle
- The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
- Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the recei
- DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data
- Posted /CAS by programmable additive latency for better mand and data bus efficiency
- On-Die Termination (ODT) for better signal quality Synchronous ODT Dynamic ODT Asynchronous ODT