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DFPCOMP - Floating Point Comparator Unit

General Description

PIN clk rst en adatai[31:0] bdatai[31:0] gto eqo lto ifo TYPE Input Input Input Input Input DESCRIPTION Global system clock Global system reset Enable computing A data bus input B data bus input output A>B output output A=B output output A

Key Features

  • Full IEEE-754 compliance Single precision real format support Simple interface No programming required 1 level pipeline Results available at every clock Fully configurable Fully synthesizable, static synchronous design with no internal tri-states Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support.

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Datasheet Details

Part number DFPCOMP
Manufacturer Digital Core Design
File Size 170.88 KB
Description Floating Point Comparator Unit
Datasheet download datasheet DFPCOMP Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DFPCOMP www.DataSheet4U.com Floating Point Comparator Unit ver 2.10 OVERVIEW DELIVERABLES ♦ Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ NCSim automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses Technical documentation ◊ ◊ ◊ The DFPCOMP compares two arguments. The input numbers format is according to IEEE-754 standard. DFPCOMP supports single precision real numbers. Compare operation was pipelined up to 1 level. Input data are fed every clock cycle. The first result appears after 1 clock period latency and next results are available each clock cycle. Full IEEE-754 unordered compare function is included.