DFPCOMP
Description
Global system clock Global system reset Enable computing A data bus input B data bus input output A>B output output A=B output output A<B output output Invalid result flag All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved.
Key Features
- Full IEEE-754 compliance Single precision real format support Simple interface No programming required 1 level pipeline Results available at every clock Fully configurable Fully synthesizable, static synchronous design with no internal tri-states Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support
