Description
Global clock Watchdog clock Global reset Power On Reset User reset Data bus from program memory Data bus from int. data memory External interrupt Timer 0 input Port X input DoCDTM Debugger input Unlimited Designs license for ○ HDL Source ○ Netlist Upgrade from ○ HDL Source to Netlist ○ Single Design to Unlimited Designs output Program memory address bus output Data bus for internal data memory output RAM address bus output Data memory write output Data memory output enable output Sleep signal output Port X output output Data direction pins for Port X output DoCDTM Debugger data output output DoCDTM Clock line output Program Memory data output output Program Memory write enable All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved.
Key Features
- Software compatible with industry standard PIC16C55X
- Harvard architecture 2 times faster compared to original implementation
- 35 instructions
- 14 bit wide instruction word
- Up to 512 bytes of internal Data Memory
- Up to 64K bytes of Program Memory
- Configurable hardware stack
- Power saving SLEEP mode
- Fully synthesizable, static synchronous design with no internal tri-states
- Scan test ready
