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DRPIC166X Datasheet Preview

DRPIC166X Datasheet

High Performance Configurable 8-bit RISC Microcontroller

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DRPIC166X
High Performance Configurable
8-bit RISC Microcontroller
ver 2.15
OVERVIEW
The DRPIC166X is a low-cost, high per-
formance, 8-bit, fully static soft IP Core,
dedicated for operation with fast (typically on-
chip) dual ported memory. The core has been
designed with a special concern about low
power consumption.
DRPIC166X soft core is software-
compatible with the industry standard
PIC16C6X. It implements an enhanced
Harvard architecture (i.e. separate
instruction and data memories) with
independent address and data buses. The 14
bit program memory and 8-bit dual port data
memory allow instruction fetch and data
operations to occur simultaneously. The
advantage of this architecture is that
instruction fetch and memory transfers can be
overlapped by multi stage pipeline, so that the
next instruction can be fetched from program
memory while the current instruction is
executed with data from the data memory.
The DRPIC166X architecture is 4 times
faster compared to standard architecture. So
most instructions are executed within 1
system clock period, except the instructions
which directly operates on program counter
PC (GOTO, CALL, RETURN), this situation
require the pipeline to be cleared and
subsequently refilled. This operation takes
additional one clock cycle.
The DRPIC166X Microcontroller fits
perfectly in applications ranging from high-
All trademarks mentioned in this document
are trademarks of their respective owners.
speed automotive and appliance motor control
to low-power remote transmitters/receivers,
pointing devices and telecom processors.
Built-in power save mode make this IP perfect
for applications where power consumption is
critical.
DRPIC166X is delivered with fully automated
testbench and complete set of tests
allowing easy package validation at each
stage of SoC design flow
CPU FEATURES
Software compatible with industry standard
PIC16C6X
Pipelined Harvard architecture 4 times
faster compared to original implementation
35 – 14 bit wide instructions
Up to 512 bytes of internal Data Memory
Up to 64K bytes of Program Memory
Configurable hardware stack
Power saving SLEEP mode
Fully synthesizable, static synchronous
design with no internal tri-states
Technology independent HDL Source
Code
1.4 GHz virtual clock frequency in a 0.18u
technological process
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.




Digital Core Design

DRPIC166X Datasheet Preview

DRPIC166X Datasheet

High Performance Configurable 8-bit RISC Microcontroller

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P Ewww.DataSheet4U.com R I P H E R A L S
Four 8 bit I/O ports
Four 8-bit corresponding TRIS registers
Interrupt feature on PORTB(7:4) change
Timer 0
8-bit timer/counter
Readable and Writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt generation on timer overflow
Edge select for external clock
Timer 1
16-bit timer/counter
3-bit prescaler
Internal or external clock select
Interrupt generation on timer overflow
Timer 2
8-bit timer with prescaler
CCP – Compare-Capture-PWM
16 Bit Compare/Capture operations
10-bit resolution PWM output
USART
Asynchronous – full duplex
Synchronous – half duplex Master/Slave
Watchdog Timer
Configurable Time out period
7-bit software programmable prescaler
Dedicated independent Watchdog Clock input
Interrupt Controller
Seven individually maskable Interrupt sources
Two external interrupts – INT Port B[7:4]
change
Five internal interrupts – TIMERS 0, 1, 2,
USART
DoCD™ debug unit
Processor execution control
Run
Halt
Step into instruction
Skip instruction
Read-write all processor contents
All trademarks mentioned in this document
are trademarks of their respective owners.
Program Counter (PC)
Program Memory
Data Memory
Special Function Registers (SFRs)
Hardware Stack and Stack Pointer
Hardware execution breakpoints
Program Memory
Data Memory
Special Function Registers (SFRs)
Hardware breakpoints activated at a certain
Program address (PC)
Address by any write into memory
Address by any read from memory
Address by write into memory a required data
Address by read from memory a required data
Three wire communication interface
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC
implementation.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA
bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time
restriction except One Year license where
time of use is limited to 12 months.
Single Design license for
VHDL, Verilog source code called HDL
Source
Encrypted, or plain text EDIF called Netlist
One Year license for
Encrypted Netlist only
Unlimited Designs license for
HDL Source
Netlist
Upgrade from
Single Design to Unlimited Designs
HDL Source to Netlist
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.


Part Number DRPIC166X
Description High Performance Configurable 8-bit RISC Microcontroller
Maker Digital Core Design
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