74AUP1G00 Datasheet PDF - Diodes SINGLE 2 INPUT POSITIVE NAND GATE Specs

74AUP1G00 - SINGLE 2 INPUT POSITIVE NAND GATE

Datasheet Summary

Description

The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.

Features

Advanced Ultra Low Power (AUP) CMOS.
Supply Voltage Range from 0.8V to 3.6V.
±4 mA Output Drive at 3.0V.
Low Static Power Consumption ICC < 0.9µA.
Low Dynamic Power Consumption CPD = 6pF (Typical at 3.6V).
Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise and fall time. The hysteresis is typically 250mV at VCC = 3.0V.
IOFF Supports Partial-Power-Down Mode Operation.
ESD Protection Exceed.

Datasheet Details

Part number	74AUP1G00
Manufacturer	DIODES
File Size	329.36 KB
Description	SINGLE 2 INPUT POSITIVE NAND GATE
Datasheet	74AUP1G00 Datasheet
Additional preview pages of the 74AUP1G00 datasheet.

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Full PDF Text Transcription

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74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. Pin Assignments The 74AUP1G00 is a single two-input positive NAND gate with a standard push-pull output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing damaging current backflow when the device is powered down. The gate performs the positive Boolean function: Y = A • B or Y = A + B Features • Advanced Ultra Low Power (AUP) CMOS • Supply Voltage Range from 0.8V to 3.6V • ±4 mA Output Drive at 3.0V • Low Static Power Consumption ICC < 0.

Published: Jul 25, 2015 |