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74HC595T16 - 8-BIT SHIFT REGISTER

Download the 74HC595T16 datasheet PDF. This datasheet also covers the 74HC595 variant, as both devices belong to the same 8-bit shift register family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC595 is an high speed CMOS device.

An eight bit shift register accpets data from the serial input (DS) on each positive transition of the shift register clock (SHCP).

When asserted low the reset function ( ) sets all shift register values to zero and is indepent of all clocks.

Key Features

  • Wide Supply Voltage Range from 2.0V to 6.0V.
  • Sinks or Sources 8mA at VCC = 4.5V.
  • CMOS Low Power Consumption.
  • Schmitt Trigger Action at All Inputs.
  • Inputs Accept up to 6.0V.
  • ESD Protection Tested per JESD 22.
  • Exceeds 200-V Machine Model (A115-A).
  • Exceeds 2000-V Human Body Model (A114-A).
  • Exceeds 1000-V Charged Device Model (C101C).
  • Latch-Up Exceeds 250mA per JESD 78, Class II.
  • Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2).
  • Halo.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC595-Diodes.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC595 8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER Description The 74HC595 is an high speed CMOS device. An eight bit shift register accpets data from the serial input (DS) on each positive transition of the shift register clock (SHCP). When asserted low the reset function ( ) sets all shift register values to zero and is indepent of all clocks. Data from the input serial shift register is placed in the output register with a rising pulse on the storages resister clock (STCP). With the output enable ( E asserted low the 3-state outputs Q0-Q7 become active and present th All registers capture data on rising edge and change output on the falling edge. If both clocks are connected together the input shift register is always one clock cycle ahead of the output register.