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PI6CG182Q Datasheet

2-Output PCIe Gen 4 Clock Generator

No Preview Available !

Pb
Lead-free Green
A product Line of
Diodes Incorporated
PI6CG182Q
2-Output PCIe Gen 4 Clock Generator for Automotive Applications
Features
ÎÎ1.8V supply voltage
ÎÎCrystal/CMOS input: 25 MHz
ÎÎ2 differential low power HCSL outputs with on-chip
termination
ÎÎIndividual output enable
ÎÎReference CMOS output
ÎÎProgrammable Slew rate and output amplitute for each
output
ÎÎDifferential outputs blocked until PLL is locked
ÎÎSelectable 0%, -0.25% or -0.5% spread on differential outputs
ÎÎStrapping pins or SMBus for configuration;
ÎÎ3.3V tolerant SMBus interface support
ÎÎVery low jitter outputs
ššDifferential cycle-to-cycle jitter <50ps
ššDifferential output-to-output skew <50ps
ššPCIe Gen1/Gen2/Gen3/Gen4 compliant
ššCMOS REFOUT phase jitter is < 1.5ps RMS
ÎÎAEC-Q 100 qualified, Automotive Grade 2 support
ÎÎTotally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
ÎÎHalogen and Antimony Free. “Green” Device (Note 3)
ÎÎPackaging (Pb-free & Green): 24-lead 4×4mm TQFN
Description
The PI6CG182Q is an 2-output very low power PCIe Gen1/Gen2/
Gen3/ Gen4 clock generator. It uses 25MHz crystal or CMOS ref-
erence as an input to generate the 100MHz low power differential
HCSL outputs with on-chip terminations. The on-chip termina-
tion can save 8 external resistors and make layout easier. An ad-
ditional buffered reference output is provided to serve as a low
noise reference for other circuitry.
It uses Diodes' proprietary PLL design to achieve very low jitter
that meets PCIe Gen1/Gen2/Gen3/Gen4 requirements. It also
provides various options such as different slew rate and ampli-
tude through strapping pins or SMBUS so that users can config-
ure the device easily to get the optimized performance for their
individual boards. The device also supports selectable spread-
spectrum options to reduce EMI for Automotive applications.
Pin Configuration
Block Diagram
OE[1:0]#
XTAL_IN/CLK
XTAL_OUT
SCLK
SDATA
SADR
SS_SEL_TRI
PD#
OSC
PLL
SS
CTRL
LOGIC
REFOUT
Q1
Q0
XTAL_IN/CLK
XTAL_OUT
VDD_OSC
SADR/REFOUT
GND_REFOUT
GND_DIG
24 23 22 21 20 19
1 18
2 17
3 GND 16
4 15
5 14
6 13
7 8 9 10 11 12
Q1-
Q1+
VDDA
GNDA
Q0-
Q0+
Notes:      
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.
2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm
antimony compounds.
PI6CG182Q
Document Number DS41704 Rev 1-2
www.diodes.com
January 2019
1 Diodes Incorporated


Diodes Semiconductor Electronic Components Datasheet

PI6CG182Q Datasheet

2-Output PCIe Gen 4 Clock Generator

No Preview Available !

A product Line of
Diodes Incorporated
PI6CG182Q
Pin Description
Pin #
1
2
3
Pin Name
XTAL_IN/CLK
XTAL_OUT
VDD_OSC
4 SADR/REFOUT
5 GND_REFOUT
6 GND_DIG
7 VDD_DIG
8 SCLK
9 SDATA
10, 21
11, 20
GND
VDDO
12 OE0#
13 Q0+
14 Q0-
15 GNDA
16 VDDA
17 Q1+
18 Q1-
19 OE1#
22 PD#
23 SS_SEL_TRI
24 GND_XTAL
Type
Description
Input
Crystal input or CMOS reference input
Output
Crystal output
Power
Power supply for oscillator circuitry, nominal 1.8V
Input/
Output
CMOS
Latch to select SMBus Address or 1.8V LVCMOS REFOUT. This pin has an
internal pull-down.
Power
Ground for REFOUT
Power
Ground for digital circuitry
Power
Power supply for digital circuitry, nominal 1.8V
Input CMOS SMBUS clock input, 3.3V tolerant
Input/
Output
CMOS SMBUS Data line, 3.3V tolerant
Power
Ground
Power
Power supply for differential outputs
Input
CMOS
Active low input for enabling Q0 pair. This pin has an internal pull-down. 1
=disable outputs, 0 = enable outputs
Output HCSL Differential true clock output
Output HCSL Differential complementary clock output
Power
Ground for analog circuitry
Power
Power supply for analog circuitry
Output HCSL Differential true clock output
Output HCSL Differential complementary clock output
Input
CMOS
Active low input for enabling Q1 pair. This pin has an internal pull-down. 1
=disable outputs, 0 = enable outputs
Input
CMOS
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
Input
Tri-level
Latched select input to select spread spectrum amount at initial power up
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
Power
Ground for oscillator circuit
PI6CG182Q
Document Number DS41704 Rev 1-2
www.diodes.com
January 2019
2 Diodes Incorporated


Part Number PI6CG182Q
Description 2-Output PCIe Gen 4 Clock Generator
Maker Diodes
Total Page 18 Pages
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