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PI6CG182Q - 2-Output PCIe Gen 4 Clock Generator

General Description

The PI6CG182Q is an 2-output very low power PCIe Gen1/Gen2/ Gen3/ Gen4 clock generator.

It uses 25MHz crystal or CMOS reference as an input to generate the 100MHz low power differential HCSL outputs with on-chip terminations.

Key Features

  • ÎÎ1.8V supply voltage ÎÎCrystal/CMOS input: 25 MHz ÎÎ2 differential low power HCSL outputs with on-chip termination ÎÎIndividual output enable ÎÎReference CMOS output ÎÎProgrammable Slew rate and output amplitute for each output ÎÎDifferential outputs blocked until PLL is locked ÎÎSelectable 0%, -0.25% or -0.5% spread on differential outputs ÎÎStrapping pins or SMBus for configuration; ÎÎ3.3V tolerant SMBus interface support ÎÎVery low jitter outputs ššDifferential cycle-to-cycle jitter.

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Other Datasheets by Diodes Incorporated

Part Number Description
PI6CG18200 Very Low Power 2-Output PCIe Clock Generator
PI6CG184Q 4-Output PCIe Gen 4 Clock Generator
PI6CG188Q 8-Output PCIe Gen 4 Clock Generator
PI6CG15401 Ultra Low Power 4-Output PCIe Clock Generator
PI6CG33201C 3.3V Very Low Power 2-Output PCIe Clock Generator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Pb Lead-free Green A product Line of Diodes Incorporated PI6CG182Q 2-Output PCIe Gen 4 Clock Generator for Automotive Applications Features ÎÎ1.8V supply voltage ÎÎCrystal/CMOS input: 25 MHz ÎÎ2 differential low power HCSL outputs with on-chip termination ÎÎIndividual output enable ÎÎReference CMOS output ÎÎProgrammable Slew rate and output amplitute for each output ÎÎDifferential outputs blocked until PLL is locked ÎÎSelectable 0%, -0.25% or -0.5% spread on differential outputs ÎÎStrapping pins or SMBus for configuration; ÎÎ3.3V tolerant SMBus interface support ÎÎVery low jitter outputs ššDifferential cycle-to-cycle jitter <50ps ššDifferential output-to-output skew <50ps ššPCIe Gen1/Gen2/Gen3/Gen4 compliant ššCMOS REFOUT phase jitter is < 1.