F50D4G41XB
FEATURES
- Voltage Supply: 1.8V (1.7 V ~ 1.95V)
- Single-level cell (SLC) technology
- Organization
- Page size x1: 4352 bytes (4096 + 256 bytes)
- Block size: 64 pages (256K + 16K bytes)
- Plane size: 1 x 2048 blocks
- Standard and extended SPI-patible serial bus interface
- Instruction, address on 1 pin; data out on 1, 2, or 4 pins
- Instruction on 1 pin; address, data out on 2 or 4 pins
- Instruction, address on 1 pin; data in on 1 or 4 pins
- Continuous read within block, configure-able by feature register
- User-selectable internal ECC supported
- 8 bits/sector
- Array performance
- 83 MHz clock frequency (MAX)
- Page read: 30μs (MAX) with on-die ECC disabled; 135μs (MAX) with on-die ECC enabled
- Page program: 200μs (TYP) with on-die ECC disabled;
240μs (TYP) with on-die ECC enabled
- Block erase: 2ms (TYP)
- Advanced features
- Read page cache mode (x2, x4, Dual, Quad, and Random)
- Read unique ID
- Device initialization
- Automatic device initialization after power-up
-...
