| Title | |
| Description | Ball Name Type CK_t, CK_c Input CKE Input CS_n CA[n:0] DQ[n:0] Input Input I/O DQS[n:0]_t, I/O DQS[n:0]_c DM[n:0] Input M54D2G16128A Function Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK_t. Single Data Rate (SDR) inputs, CS_n and CKE, are sampled at the positive Clock edge. Clock is define... |
| Features |
JEDEC LPDDR2‐S4B compliance HSUL_12 interface (High Speed Unterminated Logic 1.2V) Power supply: - VDD1 = 1.7 to 1.95V - VDD2, VDDCA, VDDQ = 1.14 to 1.3V 4n prefetch architecture Multiplexed, double data rate, command/address inputs; commands entered on every CK edge Bidirectional/differential data strobe per byte of data (DQS_t/DQS_c) ... |
| Datasheet |
 M54D2G16128A Datasheet - 5.71MB |
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