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54LS93 Datasheet Preview

54LS93 Datasheet

DIVIDE-BY-SIXTEEN COUNTER

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93
54/7493A
54LS/74LS93
DIVIDE-BY-SIXTEEN COUNTER
CONNECTION DIAGRAM
PINOUT A
DESCRIPTION — The ’93 is a 4-stage ripple counter containing a high speed
flip-flop acting as a divide-by-two and three flip-flops connected as a divide-
by-eight. HIGH signals on the Master Reset (MR) inputs override the clocks
and force all outputs to the LOW state.
ORDERING CODE: See Section 9
PKGS
PIN
OUT
COMMERCIAL GRADE
Vcc = +5.0 V ±5%,
Ta = 0°C to +70° C
MILITARY GRADE
Vcc = +5.0 V ±10%,
Ta = -55° C to +125° C
PKG
TYPE
Plastic
DIP (P)
A 7493APC, 74LS93PC
9A
Ceramic
DIP (D)
A 7493ADC, 74LS93DC 5493ADM, 54LS93DM
6A
Flatpak
(F)
A 7493AFC, 74LS93FC
5493AFM, 54LS93FM
3I
LOGIC SYMBOL
Vcc = Pin 5
GND = Pin 10
NC = Pins 4, 6, 7, 13
INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions
PIN NAMES
DESCRIPTION
CPo
CPi
MRi, MR2
Qo
-s-2 Section Clock Input
(Active Falling Edge)
-^-5 Section Clock Input
(Active Falling Edge)
Asynchronous Master Reset Inputs
(Active HIGH)
-j-2 Section Output*
Qi — Q3
+Q Section Outputs
54/74 (U.L.)
HIGH/LOW
2.0/2.0
2.0/2.0
1.0/1.0
20/10
20/10
*The Qo output is guaranteed to drive the full rated fan-out plus the CPi input.
54/74LS (U.L.)
HIGH/LOW
1.0/1.5
1.0/1.0
0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)




ETC

54LS93 Datasheet Preview

54LS93 Datasheet

DIVIDE-BY-SIXTEEN COUNTER

No Preview Available !

93
FUNCTIONAL DESCRIPTION — The ’93 is a 4-bit ripple type binary counter. It consists of four master/slave
flip-flops which are internally connected to provide a divide-by-two section and a divide-by-eight section. Each
section has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW clock
transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays.
Therefore, decoded output signals aresubject to decoding spikes and should not beused forelocks or strobes.
The Qo output of each device is designed and specified to drive the rated fan-out plus the CPi input of the
device. A gated AND asynchronous Master Reset (MRi, MR2) is provided which overrides the clocks and resets
(clears) all the flip-flops. Since the output from the divide-by-two section is not internally connected to the
succeeding stages, the devices may be operated in various counting modes.
A. 4-Bit Ripple Counter— The output Qo must be externally connected to input CP1. The input count pulses
are applied to input CPo. Simultaneous divisions Of 2,4,8, and 16 are performed at the Qo, Q1, Q2, and Q3
outputs as shown in the Truth Table.
B. 3-Bit Ripple Counter — The input cou nt pulses are applied to input CP1. Simultaneous frequency divisions
of 2, 4, and 8 are available at the Q1, Q2, and Q3 outputs. Independent use of the first flip-flop is available
if the reset function coincides with reset of the 3-bit ripple-through counter.
MODE SELECTION
RESET
INPUTS
OUTPUTS
MR1 MR2
HH
LH
HL
LL
LLLL
Count
Count
Count
H = HIGH Voltage Level
L = LOW Voltage Level
LOGIC DIAGRAM
TRUTH TABLE
OUTPUTS
COUNT
Qo Q1 Q2 03
0 LLLL
1 HL L L
2 L HL L
3 HHL L
4 L L HL
5 HL HL
6 L HHL
7 HHHL
8 LLLH
9 HL L H
10 L H L H
11 H H L H
12 L L H H
13 H L H H
14 L H H H
15 H H H H
NOTE: Output Qo connected to CP1 .
CPo
CP1
MR1
MR2
Qo
Q1
Q2
03



Part Number 54LS93
Description DIVIDE-BY-SIXTEEN COUNTER
Maker ETC
Total Page 3 Pages
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54LS93 Datasheet PDF





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