55N03L Description
55N03L S eptember , 2002 N-Channel Logic Level E nhancement Mode Field E ffect Transistor 4 P R ODUC T S UMMAR Y F E AT UR E S VDS S 30V ID R DS (on) ( m W ) T Y P 12.5 @ VGS = 10V 55A 20 @ VGS = 4.5V S uper high dense cell design for extremely low R DS (ON). High power and current handling capability. b.Guaranteed by design, not subject to production testing.