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AR2010 - GPS Controller SoC

Key Features

  • The AR2010 controller SoC includes the following functions and capabilities: CPU: MIPS 1 class R3000 level, 32-bit RISC processor with 2 KB Instruction cache and 2 KB data cache, and up to 100 MHz CPU Clock rate Built-in 64 KB SRAM SDRAM Controller supports two SDRAM banks of 16-bit data bus Up to 32 MB address space GPS Base-band decoder with 12 channel correlators and built-in carrier/code tracking loops LCD display interface driver ADC with touch screen interface controller Supports GPIOs fo.

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Datasheet Details

Part number AR2010
Manufacturer Unknown Manufacturer
File Size 529.40 KB
Description GPS Controller SoC
Datasheet download datasheet AR2010 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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The wireless communication solution provider GPS Controller SoC AR2010 The AR2010 GPS controller SoC is a single chip integrated processor with peripherals suitable for all GPS receiver related products, GPS engine board, GPS mouse, GPS CF-card, GPS watch, GPS handheld navigator/locator, PDA with GPS receiver, add-on notebook PC and other specific designs. www.DataSheet4U.