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OZ965G Datasheet Preview

OZ965G Datasheet

High-Efficiency Inverter Controller

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OZ965
High-Efficiency Inverter Controller
FEATURES
Single-stage power conversion, requiring
only a +5 V voltage source
Reduces the number of components and
board size by 30% compared with
conventional design
Supports both floating and grounded
secondary designs
90% efficiency vs. typical 75% efficiency of
conventional designs
Internal open-lamp and short-circuit
protections
Wide dimming range
Supports multiple CCFLs
Simple and reliable 2-winding transformer
design
Eliminates leakage current when used in a
floating secondary design
Constant-frequency design eliminates
interference with LCDs
ORDERING INFORMATION
OZ965G - 16-pin plastic SOP
OZ965R - 16-pin plastic TSSOP
OZ965IG - 16-pin plastic SOP
OZ965IR - 16-pin plastic TSSOP
GENERAL DESCRIPTION
dimming function with an analog voltage or low
frequency Pulse Width Modulation (PWM)
control.
Operating Principle:
The CCFL tube, transformer secondary, and
capacitor form a resonant circuit. The OZ965
utilizes the low energy loss resonate mode
principle to deliver a very high efficiency inverter.
The OZ965 drives the transformer primary with a
variable pulse width voltage directly from the +5v
supply. The resultant primary drive current is
alternately reversing with zero-voltage-switching.
Because of the transformer leakage inductance
and the secondary resonant circuit, the
secondary voltage and current are approximately
sinusoidal. This sinusoid results in very little
harmonic emi/rfi emissions.
The OZ965 operates at a single, constant
frequency in a PWM mode. Typical operating
frequency ranges between 30 KHz to 200 KHz,
dependent upon the CCFL and transformer
characteristics. Intelligent open-lamp protection
provides design flexibility so various transformer
models/manufacturers may be used.
Its high driving capability allows the OZ965 to
drive high power MOSFETs.
The OZ965 is a single chip, high-efficiency, Cold
Cathode Fluorescent Lamp (CCFL) backlight
inverter controller whose primary function is to
convert +5 volt DC power to approximately 600
VAC. Additionally, the OZ965 performs the lamp
The single stage design results in a low cost,
reliable transformer without expensive, less
reliable secondary fold-back treatment. The
transformer does not require a more expensive
center tapped primary.
Figure 1. Typical Application Circuit
J1
5V
5V
ENA
DIM
GND
GND
1
2
3
4
5
6
100k
R1
C1
0.1u
R3
150k
R2
22
C2
22u
R4
20k
R5
15k
C3
10u
C4
0.1u
C9
0.01u
U1
1
2
3
4
REF
HCLMP
LCLMP
5
6
7
8
SCP
ADJ
FB
CMP
GND
OZ965
C8
0.1u
VDD
RT
CT
OPS
ENA
NDR
PDR
SST
16
15
14
13
12
11
10
9
C10
2.2u
R6 59.0k
470p C6
C11
0.1u
R13
510k
U2
28
17
Q1
46
35
Q2
Si4532
2
The OZ965 is available in 16-pin SOP and
TSSOP packages. It is specified over the
commercial temperature range of 0°C to +70°C,
and the industrial temperature range of -40°C to
+85°C.
2
17:2200
C5 J2
71
68p 3kv
2
HV
RTN
56
T1
C7
10u
CR3
BAV99L
R16
100k
R15
4.3k
C12
0.1u
R17
1.02k
06/20/00
Copyright 2000 by O2Micro
OZ965-SF-3.0
All Rights Reserved
Page 1
U.S. Patent #5,619,402




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OZ965G Datasheet Preview

OZ965G Datasheet

High-Efficiency Inverter Controller

No Preview Available !

OZ965
FUNCTIONAL BLOCK
DIAGRAM
Refer to the functional block diagram in Figure 2,
below, and the Pin Description Table on page 3.
Power is transferred to the transformer primary
by the N-MOSFET, driven by the MOSFET gate
driver out of pin NDR. The P-MOSFET resets the
primary field, driven by pin PDR. The usual
design results in approximately 50% duty cycle at
full lamp intensity. Terminating the NDR signal
earlier than the full brightness lamp pulse width
performs lamp dimming, using the analog
dimming. The voltages on pins HCLMP and
LCLMP set a threshold voltage for the ramp
comparator setting the maximum duty cycle for
NDR.
A pulse generator circuit creates the clock signal
with the frequency determined by an external,
constant current setting resistor (RT) and timing
capacitor (CT).
The “soft-start” circuit ensures a reliable and long
lamp life starting condition.
REF
1
2.50V
IBIAS
&
REFERENCE
POFF
“Soft start” gradually increases the energy
delivered to the secondary.
When the OZ965 is enabled at pin ENA, the
capacitor on pin SST determines the duration of
the “soft-start” period, gradually increasing the
NDR pulse width to the regulated brightness. The
“soft-start” period provides sufficient time for the
lamp to ignite.
For system reliability there are several circuit
protections provided. To ensure a controlled
output, the secondary current is monitored on pin
FB and is compared to a reference voltage on pin
ADJ. The NDR signal is shortened or lengthened
dependent upon this feedback. Protection is
provided by the resultant signal, CMP, monitoring
for a lamp removal condition. Short circuit
protection is provided at pin SCP. The OPS
signal selects either HCLMP or LCLMP providing
current protection against an “Open Lamp”
condition at start-up. The OPS signal also allows
adjustment to different transformer models.
To reduce power dissipation, the switch
(MOSFET) drive signals are “break-before-make”
with a short, fixed off time between activation of
NDR or PDR.
Vdd
16
HCLMP
2
LCLMP
3
SCP
4
Vset
+
Vmax=2.6V-Vset
-
Vmax
V
V>Vmax -- -> Vmax
Vmin<V<Vmax ->V
V<Vmin -- ->Vmin
Vmin
(fix value)
+
RAMP
COMP.
-
PULSE GEN
+
COMP
-
+
COMP
-
2.5V
0.5V
RT
15
CT
14
ADJ
5
+
EA
-
FB
6
CMP
7
GND
8
R4
70k
2.5V
R5
630k
+
COMP
-
Note:
OVP – Over Voltage Protection
SCP Short-Circuit Protection
UVL Under Voltage Lockout
SS1
t1
(slow start)
RESET
UVLO
+ 0.6V
COMP
LAMP
OPS
- ON/OFF
Vdd 13
UNDER VOLTAGE
LOCKOUT
ENABLE
ZVS
CONTROLLER
Pgate
+
COMP
-
ENA
R1
300k
12
ACTIVE
"HIGH"
1.5V
PDRV
PDR
11
OLPROT
PROTECTION
Ngate
NDRV
NDR
10
I=12uA
SS2
I=2.5uA
V_SS2
t1+t2
(slow start)
SS1 SST
POFF
R2
4K
MN1
9
Figure 2. Functional Block Diagram
OZ965-SF-3.0
Page 2


Part Number OZ965G
Description High-Efficiency Inverter Controller
Maker ETC
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OZ965G Datasheet PDF






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