1.0625 Gbits/sec Fibre
The VSC7125 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to
achieve a baud rate clock at nominally 1.0625 GHz. The clock synthesizer contains a fully monolithic PLL
which does not require any external components.
The VSC7125 accepts TTL input data as a parallel 10 bit character on the T0:9 bus which is latched into the
input latch on the rising edge of REFCLK. This data will be serialized and transmitted on the TX PECL differ-
ential outputs at a baud rate of ten times the frequency of the REFCLK input, with bit T0 transmitted ﬁrst. User
data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel speciﬁca-
tion, or an equivalent, edge rich, DC-balanced code.
Transmission Character Interface
In Fibre Channel, an encoded byte is 10 bits and is referred to as a transmission character. The 10 bit inter-
face on the VSC7125 corresponds to a transmission character. This mapping is illustrated below.
Figure 1: Transmission Order and Mapping to Fibre Channel Character
Parallel Data Bits
8B/10B Bit Position
T9 T8 T7 T6 T5 T4 T3 T2 T1 T0
j hgf i edcba
XXX1 1 1 1 1 0 0
Last Data Bit Transmitted
First Data Bit Transmitted
The VSC7125 accepts differential high speed serial inputs on the RX+/RX- pins, extracts the clock and
retimes the data. The serial bit stream should be encoded to provide DC balance and limited run length by a
Fibre Channel compatible 8B/10B transmitter or equivalent. The VSC7125 clock recovery circuitry is com-
pletely monolithic and requires no external components. For proper operation, the baud rate of the data stream
to be recovered should be within 0.01% of ten times the REFCLK frequency. For example if the REFCLK used
is 106.25MHz, then the incoming serial baud rate must be 1.0625 gigabaud +0.01%.
The retimed serial bit stream is converted into a 10-bit parallel output character. The VSC7125 provides
complementary TTL recovered clocks, RCLK and RCLKN, which are at one twentieth of the serial baud rate.
This architecture is designed to simplify demultiplexing of the 10-bit data characters into a 20-bit halfword in
the downstream controller chip. The clocks are generated by dividing down the high-speed clock which is phase
locked to the serial data. The serial data is retimed by the internal high-speed clock, and deserialized. The
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52121-0, Rev. 4.1