D0036 ILL B01.3
The XL93LC56B is ideal for high volume applications
requiring low power and low density storage. This device
uses a cost effective, space saving 8-pin package. Can-
didate applications include robotics, alarm devices, elec-
tronic locks, meters and instrumentation settings.
ENDURANCE AND DATA RETENTION
The XL93LC56B is designed for applications requiring up
to 100,000 erase/write cycles per bit. It provides 100 years
of secure data retention without power after the execution
of 100,000 write cycles.
The XL93LC56B is controlled by seven 11-bit instruc-
tions. Instructions are clocked in (serially) on the DI pin.
Each instruction begins with a logical “1” (the start bit).
This is followed by the opcode (2 bits), the address field
(8 bits), and data, if appropriate. The clock signal (SK)
may be halted at any time and the XL93LC56B will remain
in its last state. This allows full static flexibility and
maximum power conservation.
The READ instruction is the only instruction that results in
serial data on the DO pin. After the read instruction and
address have been decoded, data is transferred from the
selected memory location into a serial shift register.
(Please note that one logical “0” bit precedes the actual
output data string). The output on DO changes during the
LOW-TO-HIGH transitions of SK. (See Figure 2.)
Auto Increment Read Operations
In order to facilitate memory transfer operations, the
XL93LC56B has been designed to output a continuous
stream of memory content in response to a single read
operation instruction. To utilize this function, the system
issues a read instruction specifying a start location ad-
dress. Once the addressed byte/word has been clocked
out, the data in consecutively higher address locations is
output. The address will wrap around continuously with
CS HIGH until the Chip Select control pin is brought LOW.
This allows for single instruction data dumps to be exe-
cuted with a minimum of firmware overhead.
Write Enable (WEN)
The write enable (WEN) instruction must be executed
before any device programming can be done. When VCC
is applied, this device powers up in the write disabled
state. The device then remains in a write disabled state
until a WEN instruction is executed. Thereafter the device
remains enabled until a WDS instruction is executed or
until VCC is removed. (NOTE: Neither the WEN nor the
WDS instruction has any effect on the READ instruction.
See Figure 3.)
The WRITE instruction is followed by the address and the
8 or 16 bits of data to be written. After the last data bit has
been clocked in, and before the next rising edge of SK, CS
must be brought LOW. The falling edge of CS initiates the
self-timed programming cycle.