* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture
* Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver
* Data
D5108AFTA-5B-E Datasheet (563.70 KB)
D5108AFTA-5B-E
Elpida Memory
563.70 KB
edd5108afta-5b-e.
DATA SHEET 512M bits DDR SDRAM EDD5108AFTA (64M words × 8 bits) EDD5116AFTA (32M words × 16 bits) Specifications Density: 512M bits
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