D5108AFTA-5B-E - EDD5108AFTA-5B-E

Features

Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture.
Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver.
Data inputs, outputs, and DM are synchronized with DQS.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL.

Elpida Memory

Datasheet Details

Part number	D5108AFTA-5B-E
Manufacturer	Elpida Memory
File Size	563.70 KB
Description	EDD5108AFTA-5B-E
Datasheet	D5108AFTA-5B-E Datasheet
Additional preview pages of the D5108AFTA-5B-E datasheet.

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Full PDF Text Transcription

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DATA SHEET 512M bits DDR SDRAM EDD5108AFTA (64M words × 8 bits) EDD5116AFTA (32M words × 16 bits) Specifications • Density: 512M bits • Organization ⎯ 16M words × 8 bits × 4 banks (EDD5108AFTA) ⎯ 8M words × 16 bits × 4 banks (EDD5116AFTA) • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant) • Power supply: ⎯ DDR400: VDD, VDDQ = 2.6V ± 0.1V ⎯ DDR333, 266: VDD, VDDQ = 2.5V ± 0.2V • Data rate: 400Mbps/333Mbps/266Mbps (max.) • Four internal banks for concurrent operation • Interface: SSTL_2 • Burst lengths (BL): 2, 4, 8 • Burst type (BT): ⎯ Sequential (2, 4, 8) ⎯ Interleave (2, 4, 8) • /CAS Latency (CL): 2, 2.

Published: Nov 20, 2009 |