* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE10AD4AJFA Datasheet (270.25 KB)
EBE10AD4AJFA
Elpida Memory
270.25 KB
1gb registered ddr2 sdram dimm.
DATA SHEET www.DataSheet4U.com 1GB Registered DDR2 SDRAM DIMM EBE10AD4AJFA (128M words × 72 bits, 1 Rank) Specifications Density: 1GB .
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