* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE10EE8ACWA Datasheet (272.88 KB)
EBE10EE8ACWA
Elpida Memory
272.88 KB
1gb unbuffered ddr2 sdram dimm.
DATA SHEET www.DataSheet4U.com 1GB Unbuffered DDR2 SDRAM DIMM EBE10EE8ACWA (128M words × 72 bits, 1 Rank) Specifications Density: 1GB .
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