* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE10UE8AEFB Datasheet (273.44 KB)
EBE10UE8AEFB
Elpida Memory
273.44 KB
1gb unbuffered ddr2 sdram dimm.
PRELIMINARY DATA SHEET www.DataSheet4U.com 1GB Unbuffered DDR2 SDRAM DIMM EBE10UE8AEFB (128M words × 64 bits, 1 Rank) Specifications Densi.
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