* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE21EE8ABFA Datasheet (258.38 KB)
EBE21EE8ABFA
Elpida Memory
258.38 KB
2gb unbuffered ddr2 sdram dimm.
PRELIMINARY DATA SHEET www.DataSheet4U.com 2GB Unbuffered DDR2 SDRAM DIMM EBE21EE8ABFA (256M words × 72 bits, 2 Ranks) Specifications Dens.
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