* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
*.

Pin name A0 to A14 A10 (AP) BA0, BA1, BA2 DQ0 to DQ63 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0 to CK2 /CK0 to /CK2 DQS0 to DQS7, /DQS0 to /DQS7 DM0 to DM7 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0, ODT1 NC Function Address input Row address Column a.

EBE41UF8ABDA

EBE41AE4ABHA

EBE41AE4ACFA

EBE41AE4ACWA

EBE41AF4A1QA

EBE41AF4A1QB

EBE41EF8ABFA

EBE41FE4ABHD

EBE41FE4ABHL

EBE41FE4ABHT

EBE41FE4ACFR

EBE41FE4ACFT

EBE41FE4ACWR