* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
*.

Pin name A0 to A13 A10 (AP) BA0, BA1, BA2 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0 to /CS3 CKE0, CKE1 CK0 /CK0 DQS0 to DQS17, /DQS0 to /DQS17 DM0 to DM8 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0, ODT1 /RESET Par_In* NC NU 2 2 www.DataSheet4U.com .

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