Download the EDE1116AJBG datasheet PDF.
This datasheet also covers the EDE1108AJBG variant, as both devices belong to the same 1g bits ddr2 sdram family and are provided as variant models within a single manufacturer datasheet.
Features
- Double-data-rate architecture; two data transfers per clock cycle.
- The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
- Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
- DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
- Differential clock inputs (CK and /CK).
- DLL aligns DQ and DQS transitions with CK transi.
EDE1116AJBG Datasheet
