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EDJ2108DEBG - 2G bits DDR3 SDRAM

Product Overview

Elpida Memory

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EDJ2108DEBG 2G bits DDR3 SDRAM by Elpida Memory - Datasheet Preview — Datasheet preview – EDJ2108DEBG

Datasheet Details

Part number	EDJ2108DEBG
Manufacturer	Elpida Memory
File Size	297.00 KB
Description	2G bits DDR3 SDRAM
Datasheet	EDJ2108DEBG Datasheet
Additional preview pages of the EDJ2108DEBG datasheet.

Product details

Features

Double-data-rate architecture: two data transfers per clock cycle.
The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

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Published: Oct 17, 2014 |