* Double-data-rate architecture: two data transfers per clock cycle
* The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EDJ2116DEBG Datasheet (297.00 KB)
EDJ2116DEBG
Elpida Memory
297.00 KB
2g bits ddr3 sdram.
COVER DATA SHEET 2G bits DDR3 SDRAM EDJ2108DEBG (256M words × 8 bits) EDJ2116DEBG (128M words × 16 bits) Specifications Density: 2G bits <.
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