* Double-data-rate architecture: two data transfers per clock cycle
* The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EDJ4208EFBG Datasheet (392.78 KB)
EDJ4208EFBG
Elpida Memory
392.78 KB
512m words x 8 bits 4g bits ddr3l sdram.
COVER PRELIMINARY DATA SHEET 4G bits DDR3L SDRAM EDJ4204EFBG (1024M words × 4 bits) EDJ4208EFBG (512M words × 8 bits) EDJ4216EFBG (256M words × 16 b.
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