EMD28164PA - 8M x 16 Mobile DDR SDRAM

This EMD28164PA is 134,217,728 bits synchronous double data rate Dynamic RAM.

Each 33,554,432 bits bank is organized as 4,096 rows by 512 columns by 16 bits, fabricated with EMLSI’s high performance CMOS technology.

This device uses a double data rate architecture to achieve highspeed operation.

• 1.8V power supply, 1.8V I/O power.
• LVCMOS compatible with multiplexed address.
• Double-data-rate architecture; two data transfers per clock cycle.
• Bidirectional data strobe(DQS).
• Four banks operation.
• MRS cycle with address key programs.
• CAS latency (2, 3 & 4).
• Burst length (2, 4, 8 & 16).
• Burst type (Sequential & Interleave).
• Differential clock inputs(CK and /CK).
• EMRS cycle with address key programs. www. DataSheet4U. com.
• PASR(P.