EM44CM1688LBC sdram equivalent, double data rate sdram.
* JEDEC Standard VDD/VDDQ = 1.8V±0.1V.
* All inputs and outputs are compatible with SSTL_18
interface.
* Fully differential clock inputs (CK, /CK) operation. .
The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) wr.
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