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SLA4115 Datasheet

(SLA40000 Series) High Density Gate Array

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PF842-02
SLA40000 Series
High Density Gate Array
s OVERVIEW
q Super-high-density/speed gate array
q Operates on 3.3 and 3.0V power source
(level shifter is pre-installed)
q Raw of gates: 28 to 411k gates
(sea of gates)
The SLA 40000 series are super-high-density/speed, Sea-of-gate type CMOS gate arrays adopting the 0.45É m
process.
They consume less electricity, a feature of ASICs dedicated to 3.3V, while enabling high-speed-operation as well
as 3V/5V full swing I/F in the level shifter.
There are 2- and 3-metal layer for each of 8 models from 28,260 to 411,257 gates, satisfying customer needs for
a wide range of circuit size.
In addition, the series can be used with various I/F devices such as low noise output cells, PCI I/F revision 2.0, GTL
I/F*, JTAG*, fail/safe output* and test control input*, and have diverse applications such as small information
instrument and for image processing.
To develop high-speed/high-density circuits in a shorter period of time, the series enable diverse design techniques
to be used during development such as high accuracy simulation of interconnection resistance and blunted
waveform in addition to the conventional interconnection capacity components, and provide a new layout tool for
reducing clock skew.
s FEATURES
q Super-high density (adopting 0.45µm silicon gate CMOS with 2- and 3-metal layers)
q High-speed operation (operation delay of internal gate = 0.160ns at 3.3V, 2-input power NAND standard)
q Internal gate = 3.3 and 3.0V (2.0V single), I/O buffer = 5.0, 3.3 and 3.0V (2.0V single) (built-in level shifter)
q Low power consumption (0.80µW/MHz/BC when internal cell = 3.0V)
q Output drivability (IOL = 100µ, 1, 3, 6, 12, 24 mA when PCI = 5.0V, IOL = 100µ, 1, 2, 6, 12mA when PCI = 3.3V,
IOL = 50µ, 300µ, 600µ, 2, 4mA when 2.0V)
q RAM, PLL, IrDA*, and various function cells available
q Low noise output cell, PCI I/F, USB I/F*, LVDS*, JTAG
s PRODUCT LINEUP
Master 2-layer Metal
Features
3-layer Metal
Total BCs (Raw Gates)
Usable BCs
2-layer Metal
3-layer Metal
Number of PADs
(In Case of Micro Pitch)
Propagation
Delay
Internal Gates
Input Gates
Output Buffers
I/O Level
Input Mode
Output Mode
SLA4028 SLA4046 SLA4078 SLA4115 SLA4162 SLA4239 SLA4318 SLA4411
SLA402T SLA404T SLA407T SLA411T SLA416T SLA423T SLA431T SLA441T
28,260 46,864 78,600 115,388 162,864 239,468 318,308 411,257
14,130 22,026 35,370 51,924 70,031 95,787 127,323 164,502
24,868 39,834 62,880 86,541 122,148 167,627 222,815 287,879
116 144 184 216 256 308 352 400
(128)
(164)
(212)
(256)
(304)
(368)
(424)
(480)
tpd = 0.160ns (standard at 3.3V)
tpd = 0.400ns (standard at 5.0V) level shifter, tpd = 0.420ns (standard at 3.3V)
tpd = 1.99ns (standard at 5.0V) level shifter, tpd = 1.89ns (standard at 3.3V) CL = 50pF
CMOS, TTL, PCI, USB*, LVDS*
LVTTL, TTL, CMOS, Pull-up/Pull-down, Schmitt, 2.0/3.0/3.3/5.0V Level interface (Level shifter)
Normal, Open drain, 3-state, Bi-directional, 2.0/3.0/3.3/5.0V Level interface (Level shifter)
* Under development
1
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Epson

SLA4115 Datasheet Preview

SLA4115 Datasheet

(SLA40000 Series) High Density Gate Array

No Preview Available !

SLA40000 Series
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability
of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and,
further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical
products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no
representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products
under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the
Ministry of International Trade and Industry or other approval from another government agency.
All product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
©Seiko Epson Corporation 1998 All rights reserved.
ELECTRONIC DEVICES MARKETING DIVISION
Electronic Device Marketing Department
IC Marketing & Engineering Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624
ED International Marketing Department I (Europe & U.S.A.)
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564
ED International Marketing Department II (Asia)
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110
Electric Device Information of EPSON WWW server
http://www.epson.co.jp
2


Part Number SLA4115
Description (SLA40000 Series) High Density Gate Array
Maker Epson
Total Page 2 Pages
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