PBL 3799, PBL 3799/2
PBL 3799 is an analog Subscriber Line Interface Circuit (SLIC), which is fabricated in a
75 V bipolar, monolithic process.
The programmable, resistive feed circuit incorporates a switch mode regulator to
minimize on-chip power dissipation. A stand-by state further reduces idle power
dissipation, while allowing the supervisory functions to be active.
Tip-ring polarity is reversible without altering SLIC supervisory and voice frequency
(vf) functions. Tip and ring outputs can be set to high impedance states. These and
other operating states are activated via a parallel, four bit control word.
An external resistor controls the off-hook detector threshold current. A ground key
detector with internal reference reports tip/ring dc current unbalance. The ring trip
detector can operate with both balanced and unbalanced ringing systems. The three
detectors are read via a shared output.
Ring and test relay drivers with internal clamp diodes are provided.
The complex or real two-wire impedance is set by a scaled, lumped element
Two- to four-wire and four- to two-wire signal conversion is provided by the SLIC in
conjunction with either a conventional or a programmable CODEC/filter.
Longitudinal line voltages are suppressed by a control loop within the SLIC.
The PBL 3799 package is 28-pin, dual-in-line; 32-pin or 44-pin, j-leaded chip carrier.
The difference between PBL 3799 and PBL 3799/2 is mainly the longitudinal
12/9 11/8 14/10
CHS VQBAT CHCLK
• On-chip switch mode regulator to
minimize power dissipation
• Programmable, resistive battery feed
• Line feed characteristics independ-
ent of battery variations
• Tip-ring polarity reversal function
• Tip and ring open circuit state; tip
open with ring active state
- programmable loop current/ring
- ground key detector
- ring trip detector
• Ring and test relay drivers
• Line terminating impedance,
complex or real, set by a simple
• Hybrid function with conventional or
• 70 dB longitudinal to metallic
• 79 mA peak longitudinal current
• Idle noise < 10 dBrnC; < -80 dBup
Figure 1. Block diagram.