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EM63A165TS - 16M x 16 bit Synchronous DRAM

General Description

Table 3.

Clock: CLK is driven by the system clock.

All SDRAM input signals are sampled on the positive edge of CLK.

Key Features

  • Fast access time from clock: 4.5/5.4/5.4 ns.
  • Fast clock rate: 200/166/143 MHz.
  • Fully synchronous operation.
  • Internal pipelined architecture.
  • 4M word x 16-bit x 4-bank.
  • Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function.
  • Auto Refresh and Self Refresh.
  • 8192 refresh cycles/64ms.
  • CKE power down mode.
  • Single.

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Full PDF Text Transcription for EM63A165TS (Reference)

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EtronTech EM63A165TS Etron Confidential 16M x 16 bit Synchronous DRAM (SDRAM) Advanced (Rev 1.4, Oct. /2009) Features • Fast access time from clock: 4.5/5.4/5.4 ns • Fast...

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. /2009) Features • Fast access time from clock: 4.5/5.4/5.4 ns • Fast clock rate: 200/166/143 MHz • Fully synchronous operation • Internal pipelined architecture • 4M word x 16-bit x 4-bank • Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function • Auto Refresh and Self Refresh • 8192 refresh cycles/64ms • CKE power down mode • Single +3.3V power supply • Interface: LVTTL • 54-pin 400 mil plastic TSOP II package - Pb free and Halogen free Overview The EM63A165 SDRAM is a high-speed CMOS synchronous DRAM containing 256 Mbit

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