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PIN TSSOP-28 I/O
1 I Negative audio input for left channel.
2 I Positive audio input for left channel.
3 - High-voltage analog power supply. Not internally connected to PVCCR or
Input for controlling volume ramp rate when cycling SD or during power-up. A
FADEB 4 I logic low on this pin places the amplifier in fade mode. A logic high on this pin
allows a quick transition to the desired volume setting.
I DC voltage that sets the gain of the amplifier.
6 I Analog reference for gain control section.
7 - Analog ground for digital/analog cells in core.
8 I/O Bootstrap I/O for left channel, positive high-side FET.
9 O Class-D 1/2-H-bridge positive output for left channel.
LOUTN 10 O Class-D 1/2-H-bridge negative output for left channel.
11 I/O Bootstrap I/O for left channel, negative high-side FET.
Power supply for left channel H-bridge, not internally connected to PVCCR
- Internally generated voltage supply for left channel bootstrap capacitor.
PGNDL 14 - Power ground for left channel H-bridge.
PGNDR 15 - Power ground for right channel H-bridge.
- Internally generated voltage supply for right channel bootstrap capacitor.
PVCCR 17 - Power supply for right channel H-bridge, not connected to PVCCL or AVCC.
18 I/O Bootstrap I/O for right channel, negative high-side FET.
ROUTN 19 O Class-D 1/2-H-bridge negative output for right channel.
20 O Class-D 1/2-H-bridge positive output for right channel.
21 I/O Bootstrap I/O for right channel, positive high-side FET.
Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z,
LOW = outputs enabled). TTL logic levels with compliance to AVCC.
Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic
levels with compliance to AVCC.
24 O 4-V regulated output for use by internal cells, FADEB and MUTE pins only. Not
specified for driving other external circuitry.
DS2105 Ver1.1 Dec. 2009