XRT5683A Datasheet | Exar

FEATURES D Single 5V Supply D Receiver Input Can Be Either Balanced or Unbalanced D Up To 8.448Mbps Operation In Both Tx and Rx Directions D TTL patible Interface D Device Can Be Used as a Line Interface Unit Without Clock Recovery APPLICATIONS D T1, T2, E1 & E2 Rates, PCM Line Interface D Network Multiplexing and Terminating Equipment GENERAL DESCRIPTION The XR-T5683A is a PCM line interface chip consisting of both transmit and receive circuitry. This device is offered in a plastic dual in-line (PDIP) or in a surface mount package (SOIC). The maximum bit rate of the chip is 8.448Mbps, and the signal level to the receiver can be ORDERING INFORMATION Part No. XR-T5683AIP XR-T5683AID Package 18 Lead 300 Mil PDIP 18 Lead 300 Mil JEDEC SOIC Operating Temperature Range -40°C to +85°C -40°C to +85°C attenuated by -10d B cable loss at one-half the bit rate. At nominal supply voltage operation, the typical current consumption is 40m A. BLOCK DIAGRAM 1 PDC Positive Threshold parator TTLBuffer 11 RPOS RXDATA+ 2 RXDATA- 3 TTLBuffer Negative Threshold parator 8 RCLK 4 TTLBuffer TE Peak Detector 10 RNEG 6 TANK BIAS BIAS RVCC 9 RGND 7 TVCC 18 TPOS 17 TCLK 16 TNEG 12 TGND 14 Open Collector Driver BIAS BIAS Open Collector Driver 13 TXDATA+ 15 TXDATA- Figure 1. Block Diagram Rev. 2.01 E1995 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 1 XR-T5683A PIN CONFIGURATION PDC RXDATA+ RXDATATE BIAS TANK BIAS RGND RCLK RVCC 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 TVCC TPOS TCLK TXDATATGND TXDATA+ TNEG RPOS RNEG PDC RXDATA+ RXDATATE BIAS TANK BIAS RGND RCLK RVCC 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 TVCC TPOS TCLK TXDATATGND TXDATA+ TNEG RPOS RNEG 18 Lead PDIP (0.300”) 18 Lead SOIC (JEDEC, 0.300”) PIN DESCRIPTION Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Symbol PDC RXDATA+ RXDATATE BIAS TANK BIAS RGND RCLK RVCC RNEG RPOS TNEG TXDATA+ TGND TXDATATCLK TPOS TVCC O I I O O I O O I I O O O Type Description Peak...