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Exar Corporation
Exar Corporation

XRT82L24A Datasheet Preview

XRT82L24A Datasheet

QUAD E1 LINE TRANSCEIVER

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XRT82L24A pdf
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
AUGUST 2004
REV. 1.1.2
GENERAL DESCRIPTION
The XRT82L24A is a fully integrated Quad (four chan-
nels) short-haul line interface unit for E1(2.048Mbps)
75or 120applications. Each channel consists of a
receiver with equalizer for reliable data and clock re-
covery, and a transmitter which accepts either single
or dual-rail digital inputs for signal transmission to the
line using a low output impedance line driver. The de-
vice also includes a crystal-less jitter attenuator
which, depending on system requirements, can be
selected in the receive or transmit path through the
Host or Hardware Mode control.
XRT82L24A is a low power CMOS device operating
on a single 3.3V supply with 5V tolerant digital inputs.
FEATURES
Fully integrated quad, short-haul PCM transceivers
for E1 applications.
On Chip Receive Equalizer and Transmit Pulse
Shaper for CEPT 75and 120line terminations
On chip clock recovery circuit
Transformer or capacitor coupled receiver inputs
Crystal-less jitter attenuator can be selected in the
transmit or receive path
High receiver interference immunity
Per-channel transmit power shutdown
Tri-state transmit output capability
On chip per-channel driver failure monitoring circuit
On chip HDB3/B8ZS/AMI encoder/decoder func-
tions
Supports Gapped Clock for Multiplexer Mapper
Applications
Transmit return loss meets or exceeds ETSI 300
166 standard
Meets or exceeds specifications in ITU G.703,
G.775, G.736 and G.823; ETSI 300-166
Meets or exceeds G.783 and G.823 Jitter Specifi-
cations
3.3V or 5.0V Logic level inputs
Single +3.3V Supply Operation
New Patent# 6,313,671B1 Low Power IC I/O Buffer
APPLICATIONS
Digital cross connects (DSX-1)
Channel Banks
High speed data transmission line cards
E1 Multiplexer
Public switching systems and PBX interfaces
FIGURE 1. BLOCK DIAGRAM OF THE XRT82L24A E1 LIU (HOST MODE)
TxClk_n/RZData_n
TxPOS_n/TDATA_n
TxNEG_n
RxClk_n
RxPOS_n/RDATA_n
RxNEG_n/LCV_n
RxLOS_n
INT
RDY_DTACK
PClk/Codes
PTS1/ClkE
PTS2/SR_DR
Reset
ICT
HDB3
Encoder
MUX
Tx/Rx Jitter
Attenuator
Tx Timing
Control
Tx Pulse
Shaper
Line
Driver
Driver
Monitor
Enable/
Disable
Remote
LoopBack
Digital
LoopBack
HDB3
Decoder
MUX
Channel 0
Channel 1
Channel 2
Channel 3
Tx/Rx Jitter
Attenuator
LOS
Detect
Clock
Generator
Timing & Data
Recovery
Peak
Detector
& Slicer
Local
Analog
LoopBack
Rx
Equalizer
Test
µP Controller & Hardware Interface
TVDD_n
TTIP_n
TRing_n
TGND_n
MClk
RTIP_n
RRing_n
ADD [0:3]
D[0:7]
WR_R/W/TxOFF_0
ALE_AS/TxOFF_2
CS/TxOFF_3
RD_DS/TxOFF_1
HW/HOST
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com



Exar Corporation
Exar Corporation

XRT82L24A Datasheet Preview

XRT82L24A Datasheet

QUAD E1 LINE TRANSCEIVER

No Preview Available !

XRT82L24A pdf
XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
áç
FIGURE 2. BLOCK DIAGRAM OF THE XRT82L24A T1/E1/J LIU (HARDWARE MODE)
TxClk_n/RZData
TxPOS _n/TDATA_n
TxNEG_n
RxClk_n
RxPOS_n/RDATA_n
RxNEG_n/LCV_n
RxLOS_n
INT
RDY_DTACK
PClk/Codes
PTS1/ClkE
PTS2/SR/DR
Reset
WR_R/W/TxOFF0
ALE_AS/TxOFF2
CS/TxOFF3
RD_DS/TxOFF1
HW/HOST
ICT
One of four channels
HDB3
Encoder
MUX
Tx/Rx Jitter
Attenuator
Tx Timing
Control
Tx Pulse
Shaper
Line
Driver
Driver
Monitor
Enable/
Disable
Remote
LoopBack
Digital
LoopBack
HDB3
Decoder
MUX
Tx/Rx Jitter
Attenuator
LOS
Detect
Clock
Generator
Timing & Data
Recovery
Peak
Detector
& Slicer
Local
Analog
LoopBack
Rx
Equalizer
Test
µP Controler & Hardware Interface
TVDD_n
TTIP_n
TRing_n
TGND_n
MClk
RTIP_n
RRing_n
ADD[0]
ADD[1]
ADD[2]
ADD[3]/RxMute
D[0]/FIFOS
D[1]/LOOPEN_0
D[2]/LOOPEN_1
D[3]/LOOPEN_2
D[4]LOOPEN_3
D[5]/LOOPSEL
D[6]/RxJA
D[7]TxJA
2


Part Number XRT82L24A
Description QUAD E1 LINE TRANSCEIVER
Maker Exar Corporation
Total Page 30 Pages
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