XRT83SL30 Datasheet | Exar

.. áç MAY 2003 PRELIMINARY REV. P1.0.4 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR GENERAL DESCRIPTION The XRT83SL30 is a fully integrated single-channel short-haul line interface unit for T1(1.544Mbps) 100Ω, E1(2.048Mbps) 75Ω or 120Ω and J1 110Ω applications. In T1 applications, the XRT83SL30 can generate five transmit pulse shapes to meet the short-haul Digital Cross-Connect (DSX-1) template requirements. The XRT83SL30 provides both Serial Host microprocessor interface and Hardware Mode for programming and control. Both B8ZS and HDB3 encoding and decoding functions are included and can be disabled as required. On-chip crystal-less jitter attenuator with a 32 or 64 bit FIFO can be placed either in the receive or the transmit path with loop bandwidths of less than 3Hz. The XRT83SL30 provides a variety of loop-back and diagnostic Features as well as transmit driver short circuit detection and receive loss of signal monitoring. It supports internal impedance matching for 75Ω, 100Ω, 110Ω and 120Ω for both transmitter and receiver. For the receiver this is acplished with internal resistors or through the bination of one single fixed value external resistor and programmable internal resistors. In the absence of the power supply, the transmit output and receive input are tristated allowing for redundancy applications. The chip includes an integrated programmable clock multiplier that can synthesize T1 or E1 master clocks from a variety of external clock sources. APPLICATIONS - T1 Digital Cross-Connects (DSX-1) - ISDN Primary Rate Interface - CSU/DSU E1/T1/J1 Interface - T1/E1/J1 LAN/WAN Routers - Public switching Systems and PBX Interfaces - T1/E1/J1 Multiplexer and Channel Banks Features (See Page 2) FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL30 T1/E1/J1 LIU (HOST MODE) MCLKE1 MCLKT1 MASTER CLOCK SYNTHESIZER MCLKOUT TAOS ENABLE DRIVE MONITOR TIMING CONTROL TX FILTER & PULSE SHAPER LBO[3:0]...