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Exar Corporation

XRT83SL30 Datasheet Preview

XRT83SL30 Datasheet

SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER

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PRELIMINARY
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MAY 2003
REV. P1.0.4
GENERAL DESCRIPTION
The XRT83SL30 is a fully integrated single-channel
short-haul line interface unit for T1(1.544Mbps) 100,
E1(2.048Mbps) 75or 120and J1 110applica-
tions.
In T1 applications, the XRT83SL30 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements.
The XRT83SL30 provides both Serial Host micropro-
cessor interface and Hardware Mode for program-
ming and control. Both B8ZS and HDB3 encoding
and decoding functions are included and can be dis-
abled as required. On-chip crystal-less jitter attenua-
tor with a 32 or 64 bit FIFO can be placed either in the
receive or the transmit path with loop bandwidths of
less than 3Hz. The XRT83SL30 provides a variety of
loop-back and diagnostic features as well as transmit
driver short circuit detection and receive loss of signal
monitoring. It supports internal impedance matching
for 75Ω, 100Ω, 110and 120for both transmitter
and receiver. For the receiver this is accomplished
with internal resistors or through the combination of
one single fixed value external resistor and program-
mable internal resistors. In the absence of the power
supply, the transmit output and receive input are tri-
stated allowing for redundancy applications. The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master clocks from a va-
riety of external clock sources.
APPLICATIONS
T1 Digital Cross-Connects (DSX-1)
ISDN Primary Rate Interface
CSU/DSU E1/T1/J1 Interface
T1/E1/J1 LAN/WAN Routers
Public switching Systems and PBX Interfaces
T1/E1/J1 Multiplexer and Channel Banks
FEATURES
(See Page 2)
FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL30 T1/E1/J1 LIU (HOST MODE)
MCLKE1
MCLKT1
TPOS / TDATA
TNEG / CODES
TCLK
QRPD
RCLK
RNEG / LCV
RPOS / RDATA
NLCD
RLOS
HW/HOST
CS
INT
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
QRSS ENABLE
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
HDB3/
B8ZS
ENCODER
TAOS
ENABLE
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
DRIVE
MONITOR
LINE
DRIVER
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
LOOPBACK
ENABLE
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
LBO[3:0]
PEAK
DETECTOR
& SLICER
LOCAL
ANALOG
LOOPBACK
RX
EQUALIZER
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
EQUALIZER
CONTROL
Serial Interface
TEST
MCLKOUT
DMO
TTIP
TRING
TXON
RTIP
RRING
AISD
ICT
SDO
SCLK
SDI
RESET
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




Exar Corporation

XRT83SL30 Datasheet Preview

XRT83SL30 Datasheet

SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER

No Preview Available !

XRT83SL30
áç
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.4
PRELIMINARY
FIGURE 2. BLOCK DIAGRAM OF THE XRT83SL30 T1/E1/J1 LIU (HARDWARE MODE)
MCLKE1
MCLKT1
CLKSEL[2:0]
TXTEST[0:2]
INSBPV
TPOS / TDATA
TNEG / CODES
TCLK
QRPD
RCLK
RNEG / LCV
RPOS / RDATA
NLCD
RLOS
HW/HOST
GAUGE
JASEL1
JASEL0
RXTSEL
TXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
QRSS ENABLE
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TAOS
ENABLE
TIMING
CONTROL
DFM
DRIVE
MONITOR
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
LOOPBACK
ENABLE
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
LBO[3:0]
PEAK
DETECTOR
& SLICER
LOCAL
ANALOG
LOOPBACK
RX
EQUALIZER
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
EQUALIZER
CONTROL
TEST
HARWARE CONTROL
MCLKOUT
DMO
TTIP
TRING
TXON
RTIP
RRING
LOOP1
LOOP0
AISD
ICT
JABW
TRATIO
SR/DR
EQC[4:0]
TCLKE
RCLKE
RXMUTE
ATAOS
RESET
FEATURES
Fully integrated single-channel short-haul trans-
ceiver for E1,T1 or J1 applications
Programmable Transmit Pulse Shaper for E1,T1 or
J1 short-haul interfaces
Five fixed transmit pulse settings for T1 short-haul
applications plus a fully programmable waveform
generator for transmit output pulse shaping
High receiver interference immunity
Receive monitor mode handles 0 to 29dB resistive
attenuation along with 0 to 6dB of cable attenuation
for both T1 and E1 modes
Supports 75and 120(E1), 100(T1) and 110
(J1) applications.
Internal and/or external impedance matching for
75,100Ω, 110and 120.
Tri-State transmit output and receive input capabil-
ity for redundancy applications
Provides High Impedance for Tx and Rx during
power off
Transmit return loss meets or exceeds ETSI 300
166 standard
On-chip digital clock recovery circuit for high input
jitter tolerance
Crystal-less digital jitter attenuator with 32-bit or 64-
bit FIFO Selectable either in transmit or receive
path
On-chip frequency multiplier generates T1 or E1
Master clocks from variety of external clock sources
On-chip transmit short-circuit protection and limit-
ing, and driver fail monitor output (DMO)
Receive loss of signal (RLOS) output
On-chip HDB3/B8ZS/AMI encoder/decoder
QRSS pattern generation and detection for testing
and monitoring
Error and Bipolar Violation Insertion and Detection
Receiver Line Attenuation Indication Output in 1dB
steps
Network Loop-Code Detection for automatic Loop-
Back Activation/Deactivation
Transmit All Ones (TAOS) and In-Band Network
Loop Up and Down code generators
Supports Local Analog, Remote, Digital and Dual
Loop-Back Modes
Meets or exceeds T1 and E1 short-haul network
access specifications in ITU G.703, G.775, G.736
and G.823; TR-TSY-000499; ANSI T1.403 and
T1.408; ETSI 300-166 and AT&T Pub 62411
Supports both Hardware and serial Microprocessor
interface for programming
2


Part Number XRT83SL30
Description SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER
Maker Exar Corporation
Total Page 30 Pages
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