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XRT86VL38 Datasheet Preview

XRT86VL38 Datasheet

OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

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PRELIMINARY
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
JULY 2006
REV. P1.0.9
GENERAL DESCRIPTION
The XRT86VL38 is an eight-channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and LIU integrated
solution featuring R3 technology (Relayless,
Reconfigurable, Redundancy). The physical interface
is optimized with internal impedance, and with the
patented pad structure, the XRT86VL38 provides
protection from power failures and hot swapping.
The XRT86VL38 contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/E1/J1 signal formats.
Each Framer block contains its own Transmit and
Receive E1/J1 Framing function. There are 3
Transmit HDLC controllers per channel which
encapsulate contents of the Transmit HDLC buffers
into LAPD Message frames. There are 3 Receive
HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames
from the incoming E1/J1 data stream and write the
contents into the Receive HDLC buffers. Each framer
also contains a Transmit and Overhead Data Input
port, which permits Data Link Terminal Equipment
direct access to the outbound E1/J1 frames.
Likewise, a Receive Overhead output data port
permits Data Link Terminal Equipment direct access
to the Data Link bits of the inbound E1/J1 frames.
The XRT86VL38 fully meets all of the latest E1/J1
specifications: ANSI E1.107-1988, ANSI E1.403-
1995, ANSI E1.231-1993, ANSI E1.408-1990, AT&T
TR 62411 (12-90) TR54016, and ITU G-703, G.704,
G706 and G.733, AT&T Pub. 43801, and ETS 300
011, 300 233, JT G.703, JT G.704, JT G706, I.431.
Extensive test and diagnostic functions include Loop-
backs, Boundary scan, Pseudo Random bit
sequence (PRBS) test pattern generation,
Performance Monitor, Bit Error Rate (BER) meter,
forced error insertion, and LAPD unchannelized data
payload processing according to ITU-T standard
Q.921.
Applications and Features (next page)
FIGURE 1. XRT86VL38 8-CHANNEL DS1 (E1/J1) FRAMER/LIU COMBO
Local PCM
Highway
XRT86VL38
1 of 8-channels
Tx Serial
Clock
Tx Serial
Data In
Rx Serial
Clock
Rx Serial
Data Out
PRBS
Generator &
Analyser
External Data
Link Controller
Tx Overhead In
Rx Overhead Out
2-Frame
Slip Buffer
Elastic Store
Tx Framer
2-Frame
Slip Buffer
Elastic Store
Rx Framer
Performance
Monitor
HDLC/LAPD
Controllers
Tx LIU
Interface
LLB LB
Rx LIU
Interface
LIU &
Loopback
Control
TTIP
TRING
RTIP
RRING
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
Signaling &
Alarms
System (Terminal) Side
TxON
JTAG
DMA
Interface
Microprocessor
Interface
INT
Memory
D[7:0]
3
A[14:0]
µP
Select
Intel/Motorola µP
Configuration, Control &
Status Monitor
4 WR
ALE_AS
RD
RDY_DTACK
1:2 Turns Ratio
1:1 Turns Ratio
RxLOS
Line Side
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




Exar Corporation

XRT86VL38 Datasheet Preview

XRT86VL38 Datasheet

OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

No Preview Available !

XRT86VL38
PRELIMINARY
OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. P1.0.9
APPLICATIONS
High-Density E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems
SONET/SDH terminal or Add/Drop multiplexers (ADMs)
E1/J1 add/drop multiplexers (MUX)
Channel Service Units (CSUs): E1/J1 and Fractional E1/J1
Digital Access Cross-connect System (DACs)
Digital Cross-connect Systems (DCS)
Frame Relay Switches and Access Devices (FRADS)
ISDN Primary Rate Interfaces (PRA)
PBXs and PCM channel bank
T3 channelized access concentrators and M13 MUX
Wireless base stations
ATM equipment with integrated DS1 interfaces
Multichannel DS1 Test Equipment
E1/J1 Performance Monitoring
Voice over packet gateways
Routers
FEATURES
Eight independent, full duplex DS1 Tx and Rx Framer/LIUs
Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz
asynchronous back plane connections with jitter and wander attenuation
Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 4-channel
multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus
Programmable output clocks for Fractional E1/J1
Supports Channel Associated Signaling (CAS)
Supports Common Channel Signalling (CCS)
Supports ISDN Primary Rate Interface (ISDN PRI) signaling
Extracts and inserts robbed bit signaling (RBS)
3 Integrated HDLC controllers per channel for transmit and receive, each controller having two 96-byte
buffers (buffer 0 / buffer 1)
HDLC Controllers Support SS7
Timeslot assignable HDLC
V5.1 or V5.2 Interface
Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface
every 1 second or for a single transmission
Alarm Indication Signal with Customer Installation signature (AIS-CI)
Remote Alarm Indication with Customer Installation (RAI-CI)
Gapped Clock interface mode for Transmit and Receive.
2


Part Number XRT86VL38
Description OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
Maker Exar Corporation
Total Page 30 Pages
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