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Exar Corporation
Exar Corporation

XRT94L33 Datasheet Preview

XRT94L33 Datasheet

highly integrated SONET/SDH terminator

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XRT94L33 pdf
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333---CCCHHHAAANNNNNNEEELLL DDDSSS333///EEE333///SSSTTTSSS---111 TTTOOO SSSTTTSSS---333///SSSTTTMMM---111 MMMAAAPPPPPPEEERRR ––– AAATTTMMM RRREEEGGGIIISSSTTTEEERRRSSS
March 2007
GENERAL DESCRIPTION
FEATURES
XRT94L33
Rev 2.0.0
The XRT94L33 is a highly integrated SONET/SDH
terminator designed for E3/DS3/STS-1
mapping/de-mapping functions from either the
STS-3 or STM-1 data stream. The XRT94L33
interfaces directly to the optical transceiver
The XRT94L33 processes the section, line and
path overhead in the SONET/SDH data stream and
also performs ATM and PPP PHY-layer
processing. The processing of path overhead bytes
within the STS-1s or TUG-3s includes 64 bytes for
storing the J1 bytes. Path overhead bytes can be
accessed through the microprocessor interface or
via serial interface.
The XRT94L33 uses the internal E3/DS3 De-
Synchronizer circuit with an internal pointer leak
algorithm for clock smoothing as well as to remove
the jitter due to mapping and pointer movements.
These De-Synchronizer circuits do not need any
external clock reference for its operation.
The SONET/SDH transmit blocks allow flexible
insertion of TOH and POH bytes through both
Hardware and Software. Individual POH bytes for
the transmitted SONET/SDH signal are mapped
either from the XRT94L33 memory map or from
external interface. A1, A2 framing pattern, C1 byte
and H1, H2 pointer byte are generated.
The SONET/SDH receive blocks receive SONET
STS-3 signal or SDH STM-1 signal and perform the
necessary transport and path overhead processing.
The XRT94L33 provides a line side APS
(Automatic Protection Switching) interface by
offering redundant receive serial interface to be
switched at the frame boundary.
The XRT94L33 provides 3 Mappers for performing
STS-1/VC-3 to STS-1/DS3/E3 mapping function,
one for each STS-1/DS3/E3 framers.
A PRBS test pattern generation and detection is
implemented to measure the bit-error performance.
A general-purpose microprocessor interface is
included for control, configuration and monitoring.
APPLICATIONS
Network switches
Add/Drop Multiplexer
W-DCS Digital Cross Connect Systems
Provides DS3/ E3 mapping/de-mapping for up to
3 tributaries through SONET STS-1 or SDH AU-
3 and/or TUG-3/AU-4 containers
Generates and terminates SONET/SDH section,
line and path layers
Integrated SERDES with Clock Recovery Circuit
Provides SONET frame scrambling and
descrambling
Integrated Clock Synthesizer that generates 155
MHz and 77.76 MHz clock from an external
12.96/19.44/77.76 MHz reference clock
Integrated 3 E3/DS3/STS-1 De-Synchronizer
circuit that de-jitter gapped clock to meet
0.05UIpp jitter requirements
Access to Line or Section DCC
Level 2 Performance Monitoring for E3 and DS3
Supports mixing of STS-1E and DS3 or E3 and
DS3 tributaries
UTOPIA Level 2 interface for ATM or level 2P for
Packets
E3 and DS3 framers for both Transmit and
Receive directions
Complete Transport/Section Overhead
Processing and generation per Telcordia and
ITU standards
Single PHY and Multi-PHY operations supported
Full line APS support for redundancy
applications
Loopback support for both SONET/SDH as well
as E3/DS3/STS-1
Boundary scan capability with JTAG IEEE 1149
8-bit microprocessor interface
3.3 V ± 5% Power Supply; 5 V input signal
tolerance
-40°C to +85°C Operating Temperature Range
Available in a 504 Ball TBGA package
E Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * Fax (510) 668-7017 * www.exar.com



Exar Corporation
Exar Corporation

XRT94L33 Datasheet Preview

XRT94L33 Datasheet

highly integrated SONET/SDH terminator

No Preview Available !

XRT94L33 pdf
XRT94L33
333---CCCHHHAAANNNNNNEEELLL DDDSSS333///EEE333///SSSTTTSSS---111 TTTOOO SSSTTTSSS---333///SSSTTTMMM---111 MMMAAAPPPPPPEEERRR ––– AAATTTMMM RRREEEGGGIIISSSTTTEEERRRSSS
Block Diagram of the XRT94L33
To OC3
To F.O.
Telecom
Bus
Interface
OC3
TxRx
SONET/SDH
TOH
SONET/SDH
POH
SDH MUX
To DS3/E3
STS-1
Telecom
Bus/
T3/E3/HDLC
Intf
SONET/SDH
POH
Telecom
Bus
Interface
DS3/E3
Mapper
Jitter Attenuator
&
Clock Smoothing
DS3/E3
F ram er
Pointer
Justify
STS-1 Tx/Rx
TOH & POH
HDLC
Controller
STS-1 Channel 0
PLCP
Rev222...000...000
Boundry
Scan
M ic ro p ro c e s s o r
Interface
ATM
Processor
PPP
Processor
To DS3/E3
STS-1
Telecom
Bus/
T3/E3/HDLC
Intf
SONET/SDH
POH
Telecom
Bus
Interface
DS3/E3
Mapper
Pointer
Justify
STS-1 Tx/Rx
TOH & POH
Jitter Attenuator
&
Clock Smoothing
DS3/E3
F ram er
HDLC
Controller
STS-1 Channel 1
PLCP
ATM
Processor
PPP
Processor
UTOPIA
II/IIp
Interface
To DS3/E3
STS-1
Telecom
Bus/
T3/E3/HDLC
Intf
SONET/SDH
POH
Telecom
Bus
Interface
DS3/E3
Mapper
Pointer
Justify
STS-1 Tx/Rx
TOH & POH
Jitter Attenuator
&
Clock Smoothing
DS3/E3
F ram er
HDLC
Controller
STS-1 Channel 2
PLCP
ATM
Processor
PPP
Processor
ORDERING INFORMATION
PART NUMBER
XRT94L33IB
PACKAGE TYPE
27 x 27 504 Lead TBGA
OPERATING TEMPERATURE RANGE
-40°C to +85°C
1.0 XRT94L33 REGISTERS FOR SONET ATM/PPP APPLICATIONS
1.1 THE OVERALL REGISTER MAP WITHIN THE XRT94L33
The XRT94L33 employs a direct Addressing Scheme. The Address Locations for each of the “Register
Groups” (or Register pages) is presented in the Table below.
Table 1: The Address Register Map for the XRT94L33
ADDRESS LOCATION
0x0000 – 0x00FF Reserved
REGISTER NAME
OPERATION CONTROL BLOCK REGISTERS
DEFAULT VALUE
0x0100
Operation Control Register – Byte 3
0x00
0x0101
Operation Control Register – Byte 2
0x00
2


Part Number XRT94L33
Description highly integrated SONET/SDH terminator
Maker Exar Corporation
Total Page 30 Pages
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XRT94L33 pdf
XRT94L33 Datasheet PDF
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