FMD8C16LAx-25Ex Description
FMD8C16LAx 25Ex 512M(32Mx16) Low Power DDR SDRAM Rev. 2012 1 Document Title 512M(32Mx16) Low Power DDR SDRAM Revision History Revision No. 27th, 2012 Remark Preliminary Rev.
FMD8C16LAx-25Ex Key Features
- Functionality
- Double-data-rate architecture ; two data transfers per CLK cycle
- Bidirectional data strobe per byte data (DQS)
- No DLL ; CLK to DQS is not Synchronized
- Differential CLK inputs( CLK and /CLK )
- mands entered on each positive CLK edge
- DQS edge-aligned with data for Reads
- Four internal banks for concurrent operation
- Data masks (DM) for masking write data-one mask
- Programmable burst lengths : 2, 4, 8, 16