FMD8C16LAx-25Ex - 512M(32Mx16) Low Power DDR SDRAM

Datasheet Details

Functionality - Double-data-rate architecture ; two data transfers per CLK cycle. - Bidirectional data strobe per byte data (DQS). - No DLL ; CLK to DQS is not Synchronized. - Differential CLK inputs( CLK and /CLK ). - Commands entered on each positive CLK edge. - DQS edge-aligned with data for Reads; center-aligned with data for Writes. - Four internal banks for concurrent operation. - Data masks (DM) for masking write data-one mask per byte. - Programmable burst lengths : 2, 4, 8, 16.

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Published: Apr 8, 2019 |