74F240 Datasheet | Fairchild Semiconductor

Features - 3-STATE outputs drive bus lines or buffer memory address registers - Outputs sink 64m A (48m A mil) - 12m A source current - Input clamp diodes limit high-speed termination effects General Description The 74F240 and 74F244 are octal buffers and line drivers designed to be employed as memory and address drivers, clock drivers and bus-oriented transmitters/ receivers which provide improved PC and board density. Ordering Information Order Code 74F240SC(1) 74F240SJ(1) 74F240PC 74F244SC(1) 74F244SJ(1) 74F244MSA(1) 74F244PC Package Number Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note: 1. Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Connection Diagrams 74F244 ©1988 Fairchild Semiconductor Corporation 74F240, 74F244 Rev. 1.4 .fairchildsemi. 74F240, 74F244 Octal Buffers/Line Drivers with 3-STATE Outputs Logic Symbols IEEE/IEC 74F240 IEEE/IEC 74F244 Unit Loading/Fan Out Pin Names Description OE1, OE2 OE2 I0- I7 I0- I7 O0- O7, O0- O7 3-STATE Output Enable Input (Active LOW) 3-STATE Output Enable Input (Active HIGH) Inputs (74F240) Inputs (74F244) Outputs Note: 2. Worst-case 74F240 enabled; 74F244 disabled. U.L. HIGH/LOW 1.0 / 1.667 1.0 / 1.667 1.0 / 1.667(2) 1.0 / 2.667(2) 600 / 106.6 (80) Input IIH / IIL, Output IOH /...