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74F552 - Octal Registered Transceiver

Description

The 74F552 octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction.

Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded.

Features

  • s 8-Bit bidirectional I/O Port with handshake s Register sta.

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Full PDF Text Transcription

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74F552 Octal Registered Transceiver with Parity and Flags April 1988 Revised March 2000 74F552 Octal Registered Transceiver with Parity and Flags General Description The 74F552 octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded. The flag output will be reset when the output enable returns to HIGH after reading the output port. Each register has a separate output enable control for its 3-STATE buffer. The separate Clocks, Flags, and Enables provide considerable flexibility as I/O ports for demand-response data transfer.
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