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Fairchild Semiconductor Electronic Components Datasheet

74F620 Datasheet

Inverting Octal Bus Transceiver with 3-STATE Outputs

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April 1988
Revised August 1999
74F620 • 74F623
Inverting Octal Bus Transceiver with 3-STATE Outputs
General Description
These devices are octal bus transceivers designed for
asynchronous two-way data flow between the A and B bus-
ses. Both busses are capable of sinking 64 mA and have 3-
STATE outputs. Dual enable pins (GAB, GBA) allow data
transmission from the A bus to the B bus or from the B bus
to the A bus. The 74F620 is an inverting option of the
74F623.
Features
s Designed for asynchronous two-way data flow between
busses
s Outputs sink 64 mA
s Dual enable inputs control direction of data flow
s Guaranteed 4000V minimum ESD protection
s 74F620 is an inverting option of the 74F623
Ordering Code:
Order Number Package Number
Package Description
74F620PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F623SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F623PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
FAST® is a registered trademark of Fairchild Semiconductor Corporation
© 1999 Fairchild Semiconductor Corporation DS009577
www.fairchildsemi.com


Fairchild Semiconductor Electronic Components Datasheet

74F620 Datasheet

Inverting Octal Bus Transceiver with 3-STATE Outputs

No Preview Available !

Unit Loading/Fan Out
Pin Names
Description
GBA, GAB
A0–A7
B0–B7
Enable Inputs
A Inputs or
3-STATE Outputs
B Inputs or
3-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0
3.5/1.083
150/40
3.5/1.083
150/40
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
70 µA/0.4 mA
3 mA/64 mA
70 µA/0.4 mA
3 mA/64 mA
Functional Description
The enable inputs GAB and GBA control whether data is
transmitted from the A bus to the B bus or from the B bus to
the A bus. If both GBA and GAB are disabled (GBA HIGH
and GAB LOW), the outputs are in the high impedance
state and data is stored at the A and B busses. When GBA
is active LOW, B data is sent to the A bus. When GAB is
active HIGH, data from the A bus is sent to the B bus. If
both enable inputs are active (GBA LOW and GAB HIGH)
B data is sent to the A bus while A data is sent to the B bus.
Logic Diagrams
Function Table
Enable Inputs
Operation
GBA GAB
74F620
74F623
L L B Data to A Bus B Data to A Bus
H H A Data to B Bus A Data to B Bus
HL
Z
Z
L H B Data to A Bus, B Data to A Bus,
A Data to B Bus A Data to B Bus
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
74F620
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F623
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2


Part Number 74F620
Description Inverting Octal Bus Transceiver with 3-STATE Outputs
Maker Fairchild
PDF Download

74F620 Datasheet PDF






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